summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* Explicitly specify the ANSI version of these Win32 APIs. While these are ↵Aaron Ballman2016-06-233-9/+9
| | | | | | seemingly unrelated changes, they are all NFC because we currently default to the ANSI versions of the APIs when building for Windows. This simply makes the ANSI usage explicit. llvm-svn: 273564
* [LoopUnrollAnalyzer] Fix a bug in UnrolledInstAnalyzer::visitLoad.Michael Zolotukhin2016-06-232-1/+19
| | | | | | | | | | | When simplifying a load we need to make sure that the type of the simplified value matches the type of the instruction we're processing. In theory, we can handle casts here as we deal with constant data, but since it's not implemented at the moment, we at least need to bail out. This fixes PR28262. llvm-svn: 273562
* [AMDGPU] Enable absolute expression initializer for amd_kernel_code_t fields.Valery Pykhtin2016-06-235-23/+155
| | | | | | Differential Revision: http://reviews.llvm.org/D21380 llvm-svn: 273561
* [X86][AVX512] Added AVX512F vector sign extend testsSimon Pilgrim2016-06-231-130/+415
| | | | | | Now that Elena has confirmed that PR26474 has been fixed llvm-svn: 273560
* Allow DeadStoreElimination to track combinations of partial later wrtiesHal Finkel2016-06-232-2/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DeadStoreElimination can currently remove a small store rendered unnecessary by a later larger one, but could not remove a larger store rendered unnecessary by a series of later smaller ones. This adds that capability. It works by keeping a map, which is used as an effective interval map, for each store later overwritten only partially, and filling in that interval map as more such stores are discovered. No additional walking or aliasing queries are used. In the map forms an interval covering the the entire earlier store, then it is dead and can be removed. The map is used as an interval map by storing a mapping between the ending offset and the beginning offset of each interval. I discovered this problem when investigating a performance issue with code like this on PowerPC: #include <complex> using namespace std; complex<float> bar(complex<float> C); complex<float> foo(complex<float> C) { return bar(C)*C; } which produces this: define void @_Z4testSt7complexIfE(%"struct.std::complex"* noalias nocapture sret %agg.result, i64 %c.coerce) { entry: %ref.tmp = alloca i64, align 8 %tmpcast = bitcast i64* %ref.tmp to %"struct.std::complex"* %c.sroa.0.0.extract.shift = lshr i64 %c.coerce, 32 %c.sroa.0.0.extract.trunc = trunc i64 %c.sroa.0.0.extract.shift to i32 %0 = bitcast i32 %c.sroa.0.0.extract.trunc to float %c.sroa.2.0.extract.trunc = trunc i64 %c.coerce to i32 %1 = bitcast i32 %c.sroa.2.0.extract.trunc to float call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret %tmpcast, i64 %c.coerce) %2 = bitcast %"struct.std::complex"* %agg.result to i64* %3 = load i64, i64* %ref.tmp, align 8 store i64 %3, i64* %2, align 4 ; <--- ***** THIS SHOULD NOT BE HERE **** %_M_value.realp.i.i = getelementptr inbounds %"struct.std::complex", %"struct.std::complex"* %agg.result, i64 0, i32 0, i32 0 %4 = lshr i64 %3, 32 %5 = trunc i64 %4 to i32 %6 = bitcast i32 %5 to float %_M_value.imagp.i.i = getelementptr inbounds %"struct.std::complex", %"struct.std::complex"* %agg.result, i64 0, i32 0, i32 1 %7 = trunc i64 %3 to i32 %8 = bitcast i32 %7 to float %mul_ad.i.i = fmul fast float %6, %1 %mul_bc.i.i = fmul fast float %8, %0 %mul_i.i.i = fadd fast float %mul_ad.i.i, %mul_bc.i.i %mul_ac.i.i = fmul fast float %6, %0 %mul_bd.i.i = fmul fast float %8, %1 %mul_r.i.i = fsub fast float %mul_ac.i.i, %mul_bd.i.i store float %mul_r.i.i, float* %_M_value.realp.i.i, align 4 store float %mul_i.i.i, float* %_M_value.imagp.i.i, align 4 ret void } the problem here is not just that the i64 store is unnecessary, but also that it blocks further backend optimizations of the other uses of that i64 value in the backend. In the future, we might want to add a special case for handling smaller accesses (e.g. using a bit vector) if the map mechanism turns out to be noticeably inefficient. A sorted vector is also a possible replacement for the map for small numbers of tracked intervals. Differential Revision: http://reviews.llvm.org/D18586 llvm-svn: 273559
* [mips] Don't derive the default ABI from the CPU in the backend.Daniel Sanders2016-06-2333-95/+70
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
* [ARM] Use member initializers in ARMSubtarget. NFCIDiana Picus2016-06-231-66/+22
| | | | | | | | | Move most of the initializations in ARMSubtarget::initializeEnvironment to member initializers. Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432). llvm-svn: 273556
* [mips][ias] Integers are not registers.Daniel Sanders2016-06-232-6/+30
| | | | | | | | | | | | | | | | | | | Summary: When parseAnyRegister() encounters a symbol alias, it parses integers and adds a corresponding expression to the operand list. This is clearly wrong since the only operands that parseAnyRegister() should be accepting are registers. It's not clear why this code was added and there are no test cases that cover it. I think it might be leftover from when searchSymbolAlias() was more widely used. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21377 llvm-svn: 273555
* [llc] Remove exit-on-error flag (PR27759)Diana Picus2016-06-231-12/+4
| | | | | | | | | | | | | This flag was introduced in r269655 with the new diagnostic handler for llc. Its purpose was to keep the old behavior for some of the tests that didn't recover well after an error. Those tests have been fixed, so now it's safe to remove the flag entirely. Fixes PR27759. Differential Revision: http://reviews.llvm.org/D21368 llvm-svn: 273554
* [misched] Extend scheduler to handle unsupported featuresSimon Dardis2016-06-233-1/+53
| | | | | | | | | | | | | | | | | | | | | | | Currently isComplete = 1 requires that every instruction must be described, declared unsupported or marked as having no scheduling information for a processor. For some backends such as MIPS, this requirement entails long regex lists of instructions that are unsupported. This patch teaches Tablegen to skip over instructions that are associated with unsupported feature when checking if the scheduling model is complete. Patch by: Daniel Sanders Contributions by: Simon Dardis Reviewers: MatzeB Differential Reviewer: http://reviews.llvm.org/D20522 llvm-svn: 273551
* [AMDGPU] Remove exit-on-error in test (PR27761)Diana Picus2016-06-235-8/+12
| | | | | | | | | | | | | | | | | The exit-on-error flag was necessary in order to avoid an assertion when handling DYNAMIC_STACKALLOC nodes in SelectionDAGLegalize. We can avoid the assertion by creating some dummy nodes. This enables us to remove the exit-on-error flag on the first 2 run lines (SI), but on the third run line (R600) we would run into another assertion when trying to reserve indirect registers. This patch also replaces that assertion with an early exit from the function. Fixes PR27761. Differential Revision: http://reviews.llvm.org/D20852 llvm-svn: 273550
* [mips] Fix dext/dins definitionsSimon Dardis2016-06-232-6/+14
| | | | | | | | | | | dext and dins, along with their 'm' and 'u' variants are defined in mips64r2, not mips64. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21608 llvm-svn: 273549
* [IfConversion] Bugfix: Don't use undef flag while adding use operands.Jonas Paulsson2016-06-231-3/+16
| | | | | | | | | | | | | | | IfConversion used to always add the undef flag when adding a use operand on a newly predicated instruction. This would be an operand for the register being conditionally redefined. Due to the undef flag, the liveness of this register prior to the predicated instruction would get lost. This patch changes this so that such use operands are added only when the register is live, without the undef flag. Reviewed by Quentin Colombet. http://reviews.llvm.org/D209077 llvm-svn: 273545
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCIDiana Picus2016-06-236-25/+91
| | | | | | | | | | | | | This is a cleanup commit similar to r271555, but for ARM. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21432 llvm-svn: 273544
* [AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle ↵Craig Topper2016-06-2313-963/+713
| | | | | | and selects. llvm-svn: 273543
* [X86] Add assert to ensure only 128-bit vector types are used. 256 or ↵Craig Topper2016-06-231-0/+2
| | | | | | 512-bit would require lane handling which is missing. llvm-svn: 273542
* [modules] Good ol' JIT is gone.Vassil Vassilev2016-06-231-1/+0
| | | | llvm-svn: 273541
* Add missing include. Should fix modules builds.Vassil Vassilev2016-06-231-0/+1
| | | | llvm-svn: 273540
* [LLVM][MIPS] Introduce 64 bit atomic check in CheckAtomic.cmakeSagar Thakur2016-06-231-0/+37
| | | | | | | | | | Patch by Nitesh Jain. Summary: On some target like MIPS32 we need to explicitly link atomic library for 64 bit atomic operations. This module then can be used in LLDB (http://reviews.llvm.org/D20464) or Libcxx (http://reviews.llvm.org/D16613) for explicitly link to atomic library. Reviewers: chandlerc, beanz Differential: reviews.llvm.org/D20896 llvm-svn: 273534
* Fix doubly included headerMatt Arsenault2016-06-231-1/+0
| | | | llvm-svn: 273528
* [libFuzzer] Add standard license info and comment header to AFLDriverTest.cppVitaly Buka2016-06-231-0/+4
| | | | | | | | | | | | Summary: Add license info and brief description of file to AFLDriverTest.cpp. Reviewers: kcc, aizatsky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21487 llvm-svn: 273527
* Use C++ comments for large block comment.Eric Christopher2016-06-231-16/+17
| | | | llvm-svn: 273526
* AMDGPU: readlane/writelane do not read execMatt Arsenault2016-06-232-2/+26
| | | | llvm-svn: 273525
* Fix unused variable warning by folding the temporary into the debug statement.Eric Christopher2016-06-231-2/+2
| | | | llvm-svn: 273523
* [SCCP] Don't assume all Constants are ConstantIntDavid Majnemer2016-06-232-8/+18
| | | | | | This fixes PR28269. llvm-svn: 273521
* [ADT] Add a range variant of std::transformDavid Majnemer2016-06-231-0/+8
| | | | | | This will be used in a followup change in clang. llvm-svn: 273520
* [IRObjectFile] Try to be defensive, add a break.Davide Italiano2016-06-231-0/+1
| | | | | | Suggested by Sean Silva. llvm-svn: 273519
* Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as ↵Peter Collingbourne2016-06-238-34/+15
| | | | | | it caused pr28270. llvm-svn: 273518
* [llvm-cov] Fix a buggy lit testVedant Kumar2016-06-221-1/+1
| | | | | | | There is no check prefix for "WHOLE-FILE": this particular line was supposed to use the "ALL" prefix. llvm-svn: 273517
* [codeview] Add EFLAGS to the list of CodeView register numbersReid Kleckner2016-06-221-1/+3
| | | | llvm-svn: 273516
* AMDGPU: Fix liveness when expanding m0 loopMatt Arsenault2016-06-223-25/+89
| | | | llvm-svn: 273514
* [RS4GC] Use StringRef; NFCSanjoy Das2016-06-221-4/+3
| | | | | | Spotted during random inspection. llvm-svn: 273512
* Change that to include MCMachObjectWriter.hReid Kleckner2016-06-221-1/+1
| | | | llvm-svn: 273511
* Add one more missing MCObjectWriter.h includeReid Kleckner2016-06-221-0/+1
| | | | llvm-svn: 273510
* Fix instance of -Wdelete-incompleteReid Kleckner2016-06-221-0/+1
| | | | llvm-svn: 273508
* Prune some includes from headers and sink some inline functionsReid Kleckner2016-06-2210-23/+37
| | | | | | | | MCSymbol.h shouldn't pull in MCAssembler.h, just MCFragment.h. MCLinkerOptimizationHint.h shouldn't need MCMachObjectWriter.h. The rest is fixing the fallout. llvm-svn: 273507
* [PM]: LoopAccessInfo simple refactoringXinliang David Li2016-06-222-29/+31
| | | | | | | To make definition of mov ctors easier. Differential Revision: http://reviews.llvm.org/D21563 llvm-svn: 273506
* [pdb] Treat a stream size of ~0U as 0Reid Kleckner2016-06-221-2/+4
| | | | | | My PDBs always have this size for stream 11. Not sure why. llvm-svn: 273504
* [MachO] Finish moving fat header swap functions to MachO.hChris Bieneman2016-06-222-29/+9
| | | | | | | | This is a follow-up to r273479. At the time I wrote r273479 I didn't connect the dots that the functions I was adding had to exist somewhere. Turns out, they do. This finishes moving the functions to MachO.h. Existing MachO fat header tests like test/tools/llvm-readobj/Inputs/macho-universal-archive.x86_64.i386 execute this code. llvm-svn: 273502
* [ImplicitNullChecks] Hoist trivial depdendencies if possibleSanjoy Das2016-06-222-20/+425
| | | | | | | | | | | | | | | | | | | | | | When trying to convert a loading instruction into a FAULTING_LOAD, we sometimes face code like this: if %R10 is not null: %R9<def> = MOV32ri Immediate %R9<def, tied> = AND32rm %R9, 0x20(%R10) else: goto TRAP In these cases we would like to use the AND32rm instruction as the faulting operation by hoisting the "depedency" def-ing %R9 also above the control flow, transforming the program into: %R9<def> = MOV32ri Immediate %R9<def, tied> = FAULTING_LOAD_OP(AND32rm %R9, 0x20(%R10), FailPath: TRAP) This change teaches ImplicitNullChecks to do the above, when safe. llvm-svn: 273501
* Use shouldAssumeDSOLocal.Rafael Espindola2016-06-222-5/+21
| | | | | | With this it handle -fPIE. llvm-svn: 273499
* Extract a few variables to make 'if' smaller. NFC.Rafael Espindola2016-06-221-7/+8
| | | | llvm-svn: 273497
* AMDGPU/SI: Define an intrinsic to expose ds_swizzle_b32Changpeng Fang2016-06-223-0/+32
| | | | | | | | Reviewers: tstellarAMD, arsenm Differential Revision: http://reviews.llvm.org/D21533 llvm-svn: 273496
* [codeview] Write LF_UDT_SRC_LINE records (PR28251)Hans Wennborg2016-06-227-90/+218
| | | | | | Differential Revision: http://reviews.llvm.org/D21621 llvm-svn: 273495
* Do not require __STDC_LIMIT_MACROS and othersPawel Bylica2016-06-221-9/+6
| | | | | | | | | | | | Summary: Do not require __STDC_LIMIT_MACROS and __STDC_CONSTANT_MACROS macros to be defined globally. They are not needed for C++11 compliant standard headers. Reviewers: joerg, jyknight Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21553 llvm-svn: 273493
* [CMake] LLVM_BINARY_DIR was not being properly set in LLVMConfig.cmakeChris Bieneman2016-06-222-1/+3
| | | | | | LLVMConfig.cmake needs to set LLVM_BINARY_DIR differently based on whether or not it is the build directory or the install directory. The build directory just needs to set the value from the configuration, the install directory needs to set it to the install prefix. llvm-svn: 273479
* [MachO] Adding a few missing swapStruct functionsChris Bieneman2016-06-221-0/+14
| | | | | | These are just missing swap functions for handling endian conversion. llvm-svn: 273478
* [codeview] Fix the alignment padding that we add to list recordsReid Kleckner2016-06-222-5/+7
| | | | | | | Tweak the big-types.ll test case to catch this bug. We just need an enumerator name that doesn't have a length that is a multiple of 4. llvm-svn: 273477
* [IRObjectFile] Propagate .weak attribute correctly for ASM symbols.Davide Italiano2016-06-224-7/+16
| | | | | | | PR: 28256 Differential Revision: http://reviews.llvm.org/D21616 llvm-svn: 273474
* Update header documentation for API deliberately made publicDaniel Berlin2016-06-221-2/+3
| | | | llvm-svn: 273473
OpenPOWER on IntegriCloud