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* [COFF, ARM64] Add support for Windows ARM64 COFF formatMandeep Singh Grang2017-06-2716-5/+249
| | | | | | | | | | | | | | | | Summary: This is the llvm part of the initial implementation to support Windows ARM64 COFF format. I will gradually add more functionality in subsequent patches. Reviewers: ruiu, rnk, t.p.northover, compnerd Reviewed By: ruiu, compnerd Subscribers: aemerson, mgorny, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34705 llvm-svn: 306490
* Object: Teach irsymtab::read() to try to use the irsymtab that we wrote to disk.Peter Collingbourne2017-06-276-9/+89
| | | | | | | | Fixes PR27551. Differential Revision: https://reviews.llvm.org/D33974 llvm-svn: 306488
* Bitcode: Write the irsymtab to disk.Peter Collingbourne2017-06-2717-11/+138
| | | | | | Differential Revision: https://reviews.llvm.org/D33973 llvm-svn: 306487
* Object: Add version and producer fields to the irsymtab header. NFCI.Peter Collingbourne2017-06-272-0/+30
| | | | | | | | | These will be necessary in order to handle upgrades from old bitcode files. Differential Revision: https://reviews.llvm.org/D33972 llvm-svn: 306486
* [CGP] add specialization for memcmp expansion with only one basic blockSanjay Patel2017-06-275-163/+134
| | | | llvm-svn: 306485
* [NewPM/Inliner] Reduce threshold for cold callsites in the non-PGO caseEaswaran Raman2017-06-273-44/+120
| | | | | | Differential Revision: https://reviews.llvm.org/D34312 llvm-svn: 306484
* GlobalISel: add some more sanity-checking to MachineInstrBuilder. NFC.Tim Northover2017-06-271-1/+15
| | | | llvm-svn: 306481
* [AArch64] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-06-273-0/+57
| | | | | | | | | | | | | | | | | | | Summary: Similar to X86, it should be safe to inline callees if their target-features are a subset of the caller. This change matches GCC's inlining behavior with respect to attributes [1]. [1] https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes Reviewers: kristof.beyls, javed.absar, rengolin, t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34698 llvm-svn: 306478
* [EarlyCSE][MemorySSA] Enable MemorySSA in function-simplification pass of ↵Geoff Berry2017-06-274-4/+6
| | | | | | EarlyCSE. llvm-svn: 306477
* [Analysis] Revert r306472 changes in LoopInfo headers to fix broken builds.Eugene Zelenko2017-06-273-120/+69
| | | | llvm-svn: 306476
* [GISel]: Add G_FEXP, G_FEXP2 opcodesAditya Nandakumar2017-06-275-0/+50
| | | | | | | Also add IRTranslator support. https://reviews.llvm.org/D34710 llvm-svn: 306475
* clang-format a file.Rafael Espindola2017-06-271-59/+64
| | | | | | | It had a few inconsistent indentations that made a followup patch hard to read. llvm-svn: 306474
* re-commit r306336: Enable vectorizer-maximize-bandwidth by default.Dehao Chen2017-06-2712-68/+77
| | | | | | Differential Revision: https://reviews.llvm.org/D33341 llvm-svn: 306473
* [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-277-238/+318
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 306472
* [CGP] eliminate a sub instruction in memcmp expansionSanjay Patel2017-06-276-146/+120
| | | | | | | | | | | | | | | | | | | | | | As noted in D34071, there are some IR optimization opportunities that could be handled by normal IR passes if this expansion wasn't happening so late in CGP. Regardless of that, it seems wasteful to knowingly produce suboptimal IR here, so I'm proposing this change: %s = sub i32 %x, %y %r = icmp ne %s, 0 => %r = icmp ne %x, %y Changing the predicate to 'eq' mimics what InstCombine would do, so that's just an efficiency improvement if we decide this expansion should happen sooner. The fact that the PowerPC backend doesn't eliminate the 'subf.' might be something for PPC folks to investigate separately. Differential Revision: https://reviews.llvm.org/D34416 llvm-svn: 306471
* GlobalISel: verify that a COPY is trivial when created.Tim Northover2017-06-273-6/+11
| | | | | | | | | | | | Without this check, COPY instructions can actually be one of the generic casts in disguise. That's confusing and bad. At some point during ISel this restriction has to be relaxed since the fully selected instructions will usually use COPY for those purposes. Right now I think it's possible that relaxation occurs during RegBankSelect (hence the change there). I'm not convinced that's where it belongs long-term though. llvm-svn: 306470
* Clean up a test caseXinliang David Li2017-06-271-34/+41
| | | | llvm-svn: 306468
* Create a PHI value when merging with a known undef live-inKrzysztof Parzyszek2017-06-272-8/+54
| | | | | | Differential Revision: https://reviews.llvm.org/D34640 llvm-svn: 306466
* [WebAssembly] Only run WebAssembly objdump tests if it is enabled as a targetSam Clegg2017-06-271-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D34712 llvm-svn: 306464
* [AArch64] Performance enhancements for Cavium ThunderX2 T99Joel Jones2017-06-272-166/+1059
| | | | | | | | | | | | | | This patch enables significant performance enhancements to the Cavium ThunderX2T99 LLVM backend, as observed by running SPEC2K6, by adding more detailed scheduling information. Related Bugzilla bug: http://bugs.llvm.org/show_bug.cgi?id=32562 Patch by: steleman Differential Revision: https://reviews.llvm.org/D31801 llvm-svn: 306462
* [WebAssembly] Add support for printing relocations with llvm-objdumpSam Clegg2017-06-274-3/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D34658 llvm-svn: 306461
* [WebAssembly] Add data size and alignement to linking sectionSam Clegg2017-06-2713-72/+163
| | | | | | | | | The overal size of the data section (including BSS) is otherwise not included in the wasm binary. Differential Revision: https://reviews.llvm.org/D34657 llvm-svn: 306459
* [Hexagon] Use proper predicate register state when expanding PS_vselectKrzysztof Parzyszek2017-06-272-3/+68
| | | | llvm-svn: 306458
* [InstCombine] Propagate nsw flag when turning mul by pow2 into shift when ↵Craig Topper2017-06-272-7/+5
| | | | | | | | | | | | the constant is a vector splat or the scalar bit width is larger than 64-bits The check to see if we can propagate the nsw flag used m_ConstantInt(uint64_t*&) which doesn't work with splat vectors and has a restriction that the bitwidth of the ConstantInt must be 64-bits are less. This patch changes it to use m_APInt to remove both these issues Differential Revision: https://reviews.llvm.org/D34699 llvm-svn: 306457
* [Constants] Fix copy-pasto in llvm_unreachable message. NFCCraig Topper2017-06-271-1/+1
| | | | llvm-svn: 306456
* [CGP] simplify code to get bswap in memcmp expansion; NFCISanjay Patel2017-06-271-3/+1
| | | | llvm-svn: 306452
* [AMDGPU] Add 2 new alignbit patternsStanislav Mekhanoshin2017-06-272-0/+151
| | | | | | Differential Revision: https://reviews.llvm.org/D34655 llvm-svn: 306449
* [CodeExtractor] Prevent extraction of block involving blockaddressSerge Guelton2017-06-273-0/+106
| | | | | | | | | BlockAddress are only valid within their function context, which does not interact well with CodeExtractor. Detect this case and prevent it. Differential Revision: https://reviews.llvm.org/D33839 llvm-svn: 306448
* [AMDGPU] Simplify setcc (sext from i1 b), -1|0, ccStanislav Mekhanoshin2017-06-272-1/+321
| | | | | | | | | | | Depending on the compare code that can be either an argument of sext or negate of it. This helps to avoid v_cndmask_b64 instruction for sext. A reversed value can be further simplified and folded into its parent comparison if possible. Differential Revision: https://reviews.llvm.org/D34545 llvm-svn: 306446
* [Hexagon] Update kills in hexagon-nvj even more properly than beforeKrzysztof Parzyszek2017-06-273-36/+47
| | | | | | | Account for the fact that both, the feeder and the compare can be moved over instructions that kill registers. llvm-svn: 306443
* RenameIndependentSubregs: Fix infinite loopMatt Arsenault2017-06-272-1/+21
| | | | | | | | Apparently this replacement can really be substituting the same as the original register. Avoid restarting the loop when there's been no change in the register uses. llvm-svn: 306441
* [SROA] Fix APInt size when alloca address space is not 0Yaxun Liu2017-06-272-3/+33
| | | | | | | | SROA assumes alloca address space is 0, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D34104 llvm-svn: 306440
* [AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0Stanislav Mekhanoshin2017-06-273-2/+75
| | | | | | | | | | Also factored out function to check if a boolean is an already deserialized value which does not require v_cndmask_b32 to be loaded. Added binary logical operators to its check. Differential Revision: https://reviews.llvm.org/D34500 llvm-svn: 306439
* [CGP] add an IR builder to memcmp expansion class instead of recreating it; NFCISanjay Patel2017-06-271-19/+6
| | | | | | | This was a clean-up suggestion from: https://reviews.llvm.org/D34005 llvm-svn: 306438
* [Dominators] Use Semi-NCA instead of SLT to calculate dominatorsJakub Kuderski2017-06-271-50/+24
| | | | | | | | | | | | | | | | | | | Summary: This patch makes GenericDomTreeConstruction use the Semi-NCA algorithm instead of Simple Lengauer-Tarjan. As described in `RFC: Dynamic dominators`, Semi-NCA offers slightly better performance than SLT. What's more important, it can be extended to perform incremental updates on already constructed dominator trees. The patch passes check-all, llvm test suite and is able to boostrap clang. I also wasn't able to observe any compilation time regressions. Reviewers: sanjoy, dberlin, chandlerc, grosser Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34258 llvm-svn: 306437
* LiveRangeCalc: Slightly improve map usage; NFCMatthias Braun2017-06-272-9/+14
| | | | | | | | | - DenseMap should be faster than std::map - Use the `InsertRes = insert() if (!InsertRes.inserted)` pattern rather than the `if (!X.contains(...)) { X.insert(...); }` to save one map lookup. llvm-svn: 306436
* [InstCombine] canonicalize icmp predicate feeding selectSanjay Patel2017-06-279-63/+85
| | | | | | | | | | | | | | | | | | | | | This canonicalization was suggested in D33172 as a way to make InstCombine behavior more uniform. We have this transform for icmp+br, so unless there's some reason that icmp+select should be treated differently, we should do the same thing here. The benefit comes from increasing the chances of creating identical instructions. This is shown in the tests in logical-select.ll (PR32791). InstCombine doesn't fold those directly, but EarlyCSE can simplify the identical cmps, and then InstCombine can fold the selects together. The possible regression for the tests in select.ll raises questions about poison/undef: http://lists.llvm.org/pipermail/llvm-dev/2017-May/113261.html ...but that transform is just as likely to be triggered by this canonicalization as it is to be missed, so we're just pointing out a commutation deficiency in the pattern matching: https://reviews.llvm.org/rL228409 Differential Revision: https://reviews.llvm.org/D34242 llvm-svn: 306435
* Enable ICP for AutoFDO.Dehao Chen2017-06-271-2/+3
| | | | | | | | | | | | | | Summary: AutoFDO should have ICP enabled. Reviewers: davidxl Reviewed By: davidxl Subscribers: sanjoy, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D34662 llvm-svn: 306429
* [ProfData] Make the method threadsafeXinliang David Li2017-06-271-2/+3
| | | | llvm-svn: 306428
* [InstCombine] Add test case demonstrating that we don't propagate nsw flag ↵Craig Topper2017-06-271-0/+10
| | | | | | when converting mul by pow2 to shl when the type is larger than 64-bits. NFC llvm-svn: 306427
* [InstCombine] Add test cases to show that we don't propagate 'nsw' flags ↵Craig Topper2017-06-271-0/+20
| | | | | | when converting mul by pow2 constant to shl for splat vectors. NFC llvm-svn: 306426
* [X86][AsmParser][MS-compatability] Binary/Unary operators enhancementsCoby Tayree2017-06-272-37/+92
| | | | | | | | | | | Introducing MOD binary operator https://msdn.microsoft.com/en-us/library/hha180wt.aspx Enhancing unary operators NEG and NOT, to support more complex patterns Differential Revision: https://reviews.llvm.org/D33876 llvm-svn: 306425
* Fix incorrect comment in machine-schedulerJaved Absar2017-06-271-1/+1
| | | | | | | | | | The example code incorrectly invokes ScheduleDAGMI wherein from context it is clear it intends to invoke ScheduleDAGMILive actually. Reviewed by: Andrew Trick Differential Revision: https://reviews.llvm.org/D34675 llvm-svn: 306424
* [opt-viewer] Python 3 support in opt-diff.pyBrian Gesiak2017-06-271-2/+2
| | | | | | | | | | | | | | | | Summary: The `file()` builtin is not available in Python 3; use `open()` instead. https://docs.python.org/3.0/whatsnew/3.0.html#builtins Reviewers: anemet, davidxl, davide Reviewed By: davide Subscribers: davide, fhahn, llvm-commits Differential Revision: https://reviews.llvm.org/D34670 llvm-svn: 306423
* Change sort function used in tblgen to be strict weak orderingDavid Green2017-06-271-1/+1
| | | | | | | The windows debug is failing as the sort function is not strict weak ordering, so switch a >= to a >. llvm-svn: 306422
* Another test commitChih-Hung Hsieh2017-06-271-4/+4
| | | | llvm-svn: 306420
* [DWARF] NFC: Make string-offset handling more like address-table handling; Paul Robinson2017-06-273-14/+3
| | | | | | do the indirection and relocation all in the same method. llvm-svn: 306418
* [PatternMatch] Remove 64-bit or less restriction from m_SpecificIntCraig Topper2017-06-272-12/+5
| | | | | | | | | | Not sure why this restriction existed, but it seems like we should support any size Constant here. The particular pattern in the tests is not the only use of this matcher in the tree. There's one in CodeGenPrepare and one in InstSimplify as well. Differential Revision: https://reviews.llvm.org/D34666 llvm-svn: 306417
* [JumpThreading] Add test case that was supposed to go with r306085.Craig Topper2017-06-271-0/+125
| | | | | | Looks like I forgot to 'git add' when I submitted the commit. Thanks to Chandler for noticing. llvm-svn: 306416
* Updated and extended the information about each instruction in HSW and SNB ↵Gadi Haber2017-06-2733-5266/+9564
| | | | | | | | | | | | | | | | | | | to include the following data: •static latency •number of uOps from which the instructions consists •all ports used by the instruction Reviewers:  RKSimon zvi aymanmus m_zuckerman Differential Revision: https://reviews.llvm.org/D33897 llvm-svn: 306414
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