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* WebAssembly: fix build breakage.JF Bastien2015-07-147-12/+13
| | | | | | | | | | | | | | | Summary: processFunctionBeforeCalleeSavedScan was renamed to determineCalleeSaves and now takes a BitVector parameter as of rL242165, reviewed in http://reviews.llvm.org/D10909 WebAssembly is still marked as experimental and therefore doesn't build by default. It does, however, grep by default! I notice that processFunctionBeforeCalleeSavedScan is still mentioned in a few comments and error messages, which I also fixed. Reviewers: qcolombet, sunfish Subscribers: jfb, dsanders, hfinkel, MatzeB, llvm-commits Differential Revision: http://reviews.llvm.org/D11199 llvm-svn: 242242
* [PowerPC] Support symbolic targets in patchpointsHal Finkel2015-07-142-57/+86
| | | | | | | Follow-up r235483, with the corresponding support in PPC. We use a regular call for symbolic targets (because they're much cheaper than indirect calls). llvm-svn: 242239
* ReleaseNotes.rst: Bump version to 3.8Hans Wennborg2015-07-141-17/+5
| | | | | | The notes for 3.7 are on the 3.7 branch. llvm-svn: 242237
* Accept lower case to handle windows error messages.Rafael Espindola2015-07-141-1/+1
| | | | llvm-svn: 242236
* [InstCombine] Generalize sub of selects optimization to all BinaryOperatorsDavid Majnemer2015-07-143-26/+37
| | | | | | | This exposes further optimization opportunities if the selects are correlated. llvm-svn: 242235
* Update the trunk version to 3.8.0svn.Hans Wennborg2015-07-144-15/+15
| | | | llvm-svn: 242222
* [LAA] Turn RuntimePointerChecking into a class, start hiding things, NFCAdam Nemet2015-07-141-12/+14
| | | | | | The goal is to start hiding internal APIs. llvm-svn: 242220
* [LAA] Introduce RuntimePointerChecking::PointerInfo, NFCAdam Nemet2015-07-143-54/+67
| | | | | | | Turn this structure-of-arrays (i.e. the various pointer attributes) into array-of-structures. llvm-svn: 242219
* [LAA] Lift RuntimePointerCheck out of LoopAccessInfo, NFCAdam Nemet2015-07-145-176/+173
| | | | | | | | | I am planning to add more nested classes inside RuntimePointerCheck so all these triple-nesting would be hard to follow. Also rename it to RuntimePointerChecking (i.e. append 'ing'). llvm-svn: 242218
* [PowerPC] Use the ABI indirect-call protocol for patchpointsHal Finkel2015-07-145-26/+78
| | | | | | | | | | | | We used to take the address specified as the direct target of the patchpoint and did no TOC-pointer handling. This, however, as not all that useful, because MCJIT tends to create a lot of modules, and they have their own TOC sections. Thus, to call from the generated code to other generated code, you really need to switch TOC pointers. Make this work as expected, and under ELFv1, tread the address as the function descriptor address so that the correct TOC pointer can be loaded. llvm-svn: 242217
* Add support for reading members out of thin archives.Rafael Espindola2015-07-144-7/+39
| | | | | | | | | | For now the Archive owns the buffers of the thin archive members. This makes for a simple API, but all the buffers are destructed only when the archive is destructed. This should be fine since we close the files after mmap so we should not hit an open file limit. llvm-svn: 242215
* [ExecutionEngine] Re-apply r241962 with fixes for ARM.Lang Hames2015-07-142-3/+88
| | | | | | Patch by Pierre-Andre Saulais. Thanks Pierre-Andre! llvm-svn: 242213
* Add allnodes() iterator range to SelectionDAG. NFC.Pete Cooper2015-07-145-20/+20
| | | | | | | | | | | SelectionDAG already had begin/end methods for iterating over all the nodes, but didn't define an iterator_range for us in foreach loops. This adds such a method and uses it in some of the eligible places throughout the backends. llvm-svn: 242212
* Move SDNode::IROrder in to padding to save space. NFC.Pete Cooper2015-07-141-5/+5
| | | | | | | | There was a 32-bit padding gap between 'unsigned short NumOperands, NumValues;' and 'DebugLoc debugLoc. Move 'unsigned IROrder' in to that gap. This trims the size of SDNode's from 76 bytes (really 80 due to alignment) to 72 bytes. llvm-svn: 242211
* Constify parameters in SelectionDAG methods. NFCPete Cooper2015-07-142-6/+6
| | | | llvm-svn: 242210
* Remove unnecessary .getNode() in SelectionDAG. NFC.Pete Cooper2015-07-141-22/+20
| | | | | | | | The simplify_type specialisation allows us to cast directly from SDValue to an SDNode* subclass so we don't need to pass a SDNode* to cast<>. llvm-svn: 242209
* Use more foreach loops in SelectionDAG. NFCPete Cooper2015-07-141-7/+6
| | | | llvm-svn: 242208
* MIR Serialization: Serialize the machine basic block live in registers.Alex Lorenz2015-07-147-3/+93
| | | | llvm-svn: 242204
* MIR Printer: move the function 'printReg'. NFC.Alex Lorenz2015-07-141-13/+13
| | | | | | | | This commit moves the function 'printReg' towards the start of the file so that it can be used by the conversion methods in MIRPrinter and not just the printing methods in MIPrinter. llvm-svn: 242203
* GVN: use a static array instead of regenerating it each time. NFC.Tim Northover2015-07-141-1/+1
| | | | llvm-svn: 242202
* WebAssembly: add basic int/fp instruction codegen.JF Bastien2015-07-143-28/+63
| | | | | | | | | | | | Summary: This patch has the most basic instruction codegen for 32 and 64 bit int/fp. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11193 llvm-svn: 242201
* Fix NDEBUG build warningKrzysztof Parzyszek2015-07-141-0/+2
| | | | llvm-svn: 242200
* GVN: tolerate an instruction being replaced without existing in the leaderboardTim Northover2015-07-142-1/+33
| | | | | | | | | | | | | | Sometimes an incidentally created instruction can duplicate a Value used elsewhere. It then often doesn't end up in the leader table. If it's later removed, we attempt to remove it from the leader table and segfault. Instead we should just ignore the removal request, which won't cause any problems. The reverse situation, where the original instruction is replaced by the new one (which you might think could leave the leader table empty) cannot occur, because the incidental instruction will never be found in the first place. llvm-svn: 242199
* test-release.sh: Remove the InstallDir parameter from configure_llvmCoreHans Wennborg2015-07-141-16/+5
| | | | | | After r242187, it's never set. llvm-svn: 242194
* Fix Windows build: replace __func__ with LLVM_FUNCTION_NAMEKrzysztof Parzyszek2015-07-141-4/+5
| | | | llvm-svn: 242192
* [MMX] Use the appropriate instructions for GR64 <-> VR64 copies.Bruno Cardoso Lopes2015-07-141-2/+2
| | | | | | | | | | | | | | | MOVSDto64rr and MOV64toSDrr are defined to convert between FR64 (%xmm) <-> GR64 registers, not VR64 (%mm) <-> GR64. This is wrong. I found this by inspection and could not find a suitable testcase for it since (1) we don't handle MMX bitcasts in Peephole optimizer as to generate COPYs that (2) could be expanded back to the appropriate x86 instruction in ExpandPostRA. Switch to use the appropriate instructions: MMX_MOVD64from64rr and MMX_MOVD64to64rr here. llvm-svn: 242191
* [PowerPC] Fix the PPCInstrInfo::getInstrLatency implementationHal Finkel2015-07-1412-34/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PowerPC uses itineraries to describe processor pipelines (and dispatch-group restrictions for P7/P8 cores). Unfortunately, the target-independent implementation of TII.getInstrLatency calls ItinData->getStageLatency, and that looks for the largest cycle count in the pipeline for any given instruction. This, however, yields the wrong answer for the PPC itineraries, because we don't encode the full pipeline. Because the functional units are fully pipelined, we only model the initial stages (there are no relevant hazards in the later stages to model), and so the technique employed by getStageLatency does not really work. Instead, we should take the maximum output operand latency, and that's what PPCInstrInfo::getInstrLatency now does. This caused some test-case churn, including two unfortunate side effects. First, the new arrangement of copies we get from function parameters now sometimes blocks VSX FMA mutation (a FIXME has been added to the code and the test cases), and we have one significant test-suite regression: SingleSource/Benchmarks/BenchmarkGame/spectral-norm 56.4185% +/- 18.9398% In this benchmark we have a loop with a vectorized FP divide, and it with the new scheduling both divides end up in the same dispatch group (which in this case seems to cause a problem, although why is not exactly clear). The grouping structure is hard to predict from the bottom of the loop, and there may not be much we can do to fix this. Very few other test-suite performance effects were really significant, but almost all weakly favor this change. However, in light of the issues highlighted above, I've left the old behavior available via a command-line flag. llvm-svn: 242188
* Fix several issues with the test-release.sh scriptDan Liew2015-07-141-68/+63
| | | | | | | | | | | | | | | | | | | * Use the default install prefix (/usr/local) and use DESTDIR instead to set a temporary install location for tarballing. This is the correct way to package binary releases (otherwise the temporary install path ends up in files in the binary release). * Remove ``-disable-clang`` option. It did not work correctly (tarballing assumed phase 3 was run) and when doing a release we should always be doing a three-phased build and test. Note: Technically we should only be using DESTDIR for the third phase and use --prefix for the first and second phase because we run the built clang from phase 1 and 2 (and in general an application's behaviour may depend on the install prefix). However in the case of clang it seems to not care what the install prefix was so to simplify the script we use DESTDIR for all three stages. llvm-svn: 242187
* [Hexagon] Generate instructions for operations on predicate registersKrzysztof Parzyszek2015-07-145-0/+580
| | | | | | | Convert logical operations on general-purpose registers to the correspon- ding operations on predicate registers. llvm-svn: 242186
* [CodeGen] Force emission of personality directive if explicitly specifiedKeno Fischer2015-07-148-22/+82
| | | | | | | | | | | | | | | | | | | Summary: Before this change, personality directives were not emitted if there was no invoke left in the function (of course until recently this also meant that we couldn't know what the personality actually was). This patch forces personality directives to still be emitted, unless it is known to be a noop in the absence of invokes, or the user explicitly specified `nounwind` (and not `uwtable`) on the function. Reviewers: majnemer, rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D10884 llvm-svn: 242185
* Add support for on-disk hash table lookup with a known hash, for situations ↵Richard Smith2015-07-141-5/+11
| | | | | | where the same key will be looked up in multiple tables. llvm-svn: 242179
* Teach config.guess that MSYS exists.Yaron Keren2015-07-141-0/+3
| | | | | | | We might not want to upgrade config.guess to the current version due to the license change from GPL2 to GPL3. llvm-svn: 242178
* AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)Matt Arsenault2015-07-146-16/+117
| | | | | | | | | | | | | | | | | This can be done only with moves which theoretically will optimize better later. Although this transform increases the instruction count, it should be code size / cycle count neutral in the worst VALU case. It also seems to slightly improve a couple of testcases due to other DAG combines this exposes. This is probably slightly worse for the SALU case, so it might be better to handle this during moveToVALU, although then you lose some simplifications like the load width reducing in the simple testcase. llvm-svn: 242177
* AMDGPU/SI: Fix read2 merging into a super register.Matt Arsenault2015-07-149-28/+308
| | | | | | | | | | | | | | | | If the read2 produced was supposed to be writing into a super register, it would use the wrong subregister indices. Fix this by inserting copies, so we only ever write to a vreg_64. Run the register coalescer again to clean this up, although this isn't ideal and often does result in an extra move. Also remove the assert that offset1 > offset0. There isn't a real reason to not allow this other than a minor convenience in the compiler, and it doesn't seem worth the effort of avoiding it. llvm-svn: 242174
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-1418-179/+23
| | | | | | | | | | | | | We have a detailed def/use lists for every physical register in MachineRegisterInfo anyway, so there is little use in maintaining an additional bitset of which ones are used. Removing it frees us from extra book keeping. This simplifies VirtRegMap. Differential Revision: http://reviews.llvm.org/D10911 llvm-svn: 242173
* Avoid MSVC-incompatible use of init list.David Blaikie2015-07-141-1/+1
| | | | llvm-svn: 242170
* RAGreedy: Keep track of allocated PhysRegs internallyMatthias Braun2015-07-144-18/+40
| | | | | | | | | | | Do not use MachineRegisterInfo::setPhysRegUsed()/isPhysRegUsed() anymore. This bitset changes function-global state and is set by the VirtRegRewriter anyway. Simply use a bitvector private to RAGreedy. Differential Revision: http://reviews.llvm.org/D10910 llvm-svn: 242169
* Add missing builtins to the PPC back end for ABI compliance (vol. 4)Nemanja Ivanovic2015-07-143-0/+42
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D11183 Back end portion of the fourth round of additions to altivec.h. llvm-svn: 242167
* ARM: add at least one real test for r242123.Tim Northover2015-07-141-0/+10
| | | | | | | | The ones committed were orthogonal to the change and would have passed before that revision. What it *did* do was prevent an assertion failure when generating object files. llvm-svn: 242166
* PrologEpilogInserter: Rewrite API to determine callee save regsiters.Matthias Braun2015-07-1429-148/+242
| | | | | | | | | | | | | | | | This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan(): - Rename the function to determineCalleeSaves() - Pass a bitset of callee saved registers by reference, thus avoiding the function-global PhysRegUsed bitset in MachineRegisterInfo. - Without PhysRegUsed the implementation is fine tuned to not save physcial registers which are only read but never modified. Related to rdar://21539507 Differential Revision: http://reviews.llvm.org/D10909 llvm-svn: 242165
* AArch64: add rev64 alias for 64-bit rev instruction.Tim Northover2015-07-142-0/+5
| | | | | | | It could be useful to assembly programmers and makes the permitted variants a little more uniform. llvm-svn: 242164
* [Hexagon] Generate "extract" instructions more aggressivelyKrzysztof Parzyszek2015-07-145-14/+356
| | | | | | | Generate extract instructions (via intrinsics) before the DAG combiner folds shifts into unrecognizable forms. llvm-svn: 242163
* llvm-ar: Don't try to extract from thin archives.Rafael Espindola2015-07-143-0/+9
| | | | | | This matches the gnu ar behavior. llvm-svn: 242162
* ARMAsmParser: Take MCInst param by const-refHans Wennborg2015-07-141-8/+9
| | | | | | (Broken out from http://reviews.llvm.org/D11167) llvm-svn: 242160
* Add default value for Args parameter of IRBuilder::CreateCallDavid Blaikie2015-07-141-1/+1
| | | | | | | | Convenient for calls to zero-argument functions. Patch by servuswiegehtz at yahoo.de llvm-svn: 242159
* Sleep for 2.1 seconds to see if that makes the test stable on windows.Rafael Espindola2015-07-141-2/+3
| | | | | | Might fix pr24106. llvm-svn: 242158
* Allocate the IntervalMap in ELF.h on the heap to work around MSVC alignment ↵Hans Wennborg2015-07-141-5/+7
| | | | | | bug (PR24113) llvm-svn: 242157
* llvm-ar: print an error when the requested member is not found.Rafael Espindola2015-07-142-3/+16
| | | | llvm-svn: 242156
* Use a range loop. NFC.Rafael Espindola2015-07-141-19/+17
| | | | llvm-svn: 242153
* Revert "Fix `llvm-config` to emit the linker flag for the combined shared ↵JF Bastien2015-07-144-50/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | object built by autoconfig/make instead of the individual components." This reverts commit 01446706b4c0a86bb64768f307079cab5c514aa3. Causes breakage, seems to be related to 'svn' in the file's name: CC=gcc CXX=g++ \ ../llvm/configure \ --prefix=/usr \ --sysconfdir=/etc \ --enable-shared \ --enable-libffi \ --enable-targets=all \ --disable-assertions \ --with-python=/usr/bin/python2 \ --enable-optimized make REQUIRES_RTTI=1 ENABLE_PIC=1 results: llvm[2]: Linking Release unit test Support (without symbols) llvm[2]: ======= Finished Linking Release Unit test Support (without symbols) make[3]: Entering directory '/build/llvm-svn/src/build/bindings/ocaml/llvm' make[3]: *** No rule to make target '/build/llvm- svn/src/build/Release/lib/ocaml/libLLVM-3.7.0svn.so', needed by 'build- deplibs'. Stop. make[3]: *** Waiting for unfinished jobs.... llvm[3]: Compiling llvm_ocaml.c for Release build make[3]: Leaving directory '/build/llvm-svn/src/build/bindings/ocaml/llvm' /build/llvm-svn/src/llvm/Makefile.rules:880: recipe for target 'all' failed /build/llvm-svn/src/llvm/Makefile.rules:965: recipe for target 'all' failed Differential Revision: http://reviews.llvm.org/D10716 llvm-svn: 242152
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