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* [X86] Null out some redundant patterns for masked vector register to ↵Craig Topper2016-02-261-10/+19
| | | | | | | | register moves. These can be accomplished with both aligned and unaligned opcodes. Currently aligned is what is being used so remove the redundant patterns for the unaligned versions. But don't do this for the byte and word vector types since they don't have aligned versions. llvm-svn: 261985
* [TableGen] Fix typos in comments. NFCCraig Topper2016-02-261-2/+2
| | | | llvm-svn: 261984
* [X86] Add test cases for r261977 and fix a grammatical error.Craig Topper2016-02-262-1/+5
| | | | llvm-svn: 261983
* [JumpThreading] Simplify Instructions first in ComputeValueKnownInPredecessors()Haicheng Wu2016-02-262-20/+85
| | | | | | This change tries to find more opportunities to thread over basic blocks. llvm-svn: 261981
* [X86] Remove a couple returns after llvm_unreachables. NFCCraig Topper2016-02-261-6/+2
| | | | llvm-svn: 261979
* [X86] Use inclusive ranges for XMM/YMM/ZMM registers in is32Extended and ↵Craig Topper2016-02-261-9/+9
| | | | | | isX86_64ExtendedReg. NFC llvm-svn: 261978
* [X86] Explicitly diagnose use of %xmm16-%xmm31, %ymm16-%ymm31 and ↵Craig Topper2016-02-261-1/+7
| | | | | | %zmm16-%zmm31 when AVX512 is not enabled in the asm parser. llvm-svn: 261977
* Another fix the testcase introduced by r261903 - Add the missing matchesHongbin Zheng2016-02-261-3/+3
| | | | llvm-svn: 261971
* Minor doc fix: statepoints are invokable tooSanjoy Das2016-02-261-2/+3
| | | | llvm-svn: 261968
* MachineCopyPropagation: Catch copies of the form A<-B;A<-BMatthias Braun2016-02-264-63/+179
| | | | | | Differential Revision: http://reviews.llvm.org/D17475 llvm-svn: 261966
* MachineCopyPropagation: Keep scanning through instructions with regmasksMatthias Braun2016-02-262-59/+114
| | | | | | | | | | | | | | | | | | | | | | | This also simplifies the code by removing the overly conservative NoInterveningSideEffect() function. This function checked: - That the two copies belong to the same block: We only process one block at a time and clear our maps in between it is impossible to find a copy from a different block. - There is no terminator between the two copy instructions: This is not allowed anyway (the MachineVerifier would complain) - Does not have instructions with hasUnmodeledSideEffects() or isCall() set: Even for those instructuction we must have all clobbers/defs of registers explicit as an operand. If the register is explicitely clobbered we would never come to the point of checking for NoInterveningSideEffect() anyway. (I also checked this with a temporary build of the test-suite with all potentially failing conditions in NoInterveningSideEffect() turned into asserts) Differential Revision: http://reviews.llvm.org/D17474 llvm-svn: 261965
* [PGO] Add test case to ensure covmap section is not allocatable.Xinliang David Li2016-02-262-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D17324 llvm-svn: 261959
* [LoopUnrollAnalyzer] Check that we're using SCEV for the same loop we're ↵Michael Zolotukhin2016-02-264-5/+53
| | | | | | | | | | | | | | simulating. Summary: Check that we're using SCEV for the same loop we're simulating. Otherwise, we might try to use the iteration number of the current loop in SCEV expressions for inner/outer loops IVs, which is clearly incorrect. Reviewers: chandlerc, hfinkel Subscribers: sanjoy, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D17632 llvm-svn: 261958
* Minor code cleanups. NFC.Junmo Park2016-02-261-3/+3
| | | | llvm-svn: 261955
* [UnitTests] UnrollAnalyzer: make unit-test more general so that it can cover ↵Michael Zolotukhin2016-02-261-3/+5
| | | | | | more cases in future. llvm-svn: 261954
* [sancov] Pruning full dominator blocks from instrumentation.Mike Aizatsky2016-02-262-4/+41
| | | | | | | | | | | | | | Summary: This is the first simple attempt to reduce number of coverage- instrumented blocks. If a basic block dominates all its successors, then its coverage information is useless to us. Ingore such blocks if santizer-coverage-prune-tree option is set. Differential Revision: http://reviews.llvm.org/D17626 llvm-svn: 261949
* [x86, SSE] add tests to show missing pcmp foldsSanjay Patel2016-02-261-0/+88
| | | | llvm-svn: 261948
* Add forward declarations /NFCXinliang David Li2016-02-261-0/+3
| | | | llvm-svn: 261946
* [WinEH] Don't remove unannotated inline-asm callsDavid Majnemer2016-02-262-2/+29
| | | | | | | | Inline-asm calls aren't annotated with funclet bundle operands because they don't throw and cannot be inlined through. We shouldn't require them to bear an funclet bundle operand. llvm-svn: 261942
* More internal details of SROA pass to library visibility.Owen Anderson2016-02-251-1/+1
| | | | llvm-svn: 261934
* Support: Give ManagedStatic's helper object library visibilityJustin Bogner2016-02-251-5/+6
| | | | | | It doesn't make much sense to export these symbols. llvm-svn: 261931
* Reverts change r261907 and r261918Hemant Kulkarni2016-02-255-745/+265
| | | | llvm-svn: 261927
* Use regex in testcase, do not fail windows botsHongbin Zheng2016-02-251-10/+10
| | | | llvm-svn: 261922
* Fix endianness issue on BE machines introduced by r261907Hemant Kulkarni2016-02-251-3/+4
| | | | llvm-svn: 261918
* Reformatted a comment to fit the 80 column limit. NFC.David L Kreitzer2016-02-251-2/+2
| | | | llvm-svn: 261916
* Try to fix windows fail at r261902.Hongbin Zheng2016-02-251-0/+10
| | | | | | Introduce move constructor and move assignment operator to PostDominatorTree. llvm-svn: 261910
* [llvm-readobj] Enable GNU style sections and relocations printingHemant Kulkarni2016-02-255-265/+744
| | | | | | http://reviews.llvm.org/D17523 llvm-svn: 261907
* Introduce RegionInfoAnalysis, which compute Region Tree in the new ↵Hongbin Zheng2016-02-2522-0/+149
| | | | | | | | PassManager. NFC Differential Revision: http://reviews.llvm.org/D17571 llvm-svn: 261904
* Introduce DominanceFrontierAnalysis to the new PassManager to compute ↵Hongbin Zheng2016-02-2510-68/+137
| | | | | | | | DominanceFrontier. NFC Differential Revision: http://reviews.llvm.org/D17570 llvm-svn: 261903
* Introduce analysis pass to compute PostDominators in the new pass manager. NFCHongbin Zheng2016-02-2513-85/+124
| | | | | | Differential Revision: http://reviews.llvm.org/D17537 llvm-svn: 261902
* ARM: disallow pc as a base register in Thumb2 memory ops.Tim Northover2016-02-253-2/+18
| | | | | | | These should all be deferring to the "OP (literal)" variant according to the ARM ARM. llvm-svn: 261895
* Revert "Introduce analysis pass to compute PostDominators in the new pass ↵Hongbin Zheng2016-02-2512-120/+81
| | | | | | | | manager. NFC" This reverts commit a3e5cc6a51ab5ad88d1760c63284294a4e34c018. llvm-svn: 261891
* Revert "Introduce DominanceFrontierAnalysis to the new PassManager to ↵Hongbin Zheng2016-02-2510-137/+68
| | | | | | | | compute DominanceFrontier. NFC" This reverts commit 109c38b2226a87b0be73fa7a0a8c1a81df20aeb2. llvm-svn: 261890
* Revert "Introduce RegionInfoAnalysis, which compute Region Tree in the new ↵Hongbin Zheng2016-02-2522-149/+0
| | | | | | | | PassManager. NFC" This reverts commit 8228b4d374edeb4cc0c5fddf6e1ab876918ee126. llvm-svn: 261889
* rangify; NFCISanjay Patel2016-02-251-54/+43
| | | | llvm-svn: 261888
* [AArch64] Clean up callee-save CFI emission. NFC.Geoff Berry2016-02-252-46/+9
| | | | | | | | | | | | | | | | | | | Summary: Avoid special case for FP, LR CFI emission and just allow general AArch64FrameLowering::emitCalleeSavedFrameMoves() to handle them. Also, stop recalculating the stack offsets in emitCalleeSavedFrameMoves() since we can just reuse the previously calculated offset stored in the MachineFrameInfo. Depends on D17000 Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17004 llvm-svn: 261885
* Introduce RegionInfoAnalysis, which compute Region Tree in the new ↵Hongbin Zheng2016-02-2522-0/+149
| | | | | | | | PassManager. NFC Differential Revision: http://reviews.llvm.org/D17571 llvm-svn: 261884
* Introduce DominanceFrontierAnalysis to the new PassManager to compute ↵Hongbin Zheng2016-02-2510-68/+137
| | | | | | | | DominanceFrontier. NFC Differential Revision: http://reviews.llvm.org/D17570 llvm-svn: 261883
* Introduce analysis pass to compute PostDominators in the new pass manager. NFCHongbin Zheng2016-02-2512-81/+120
| | | | | | Differential Revision: http://reviews.llvm.org/D17537 llvm-svn: 261882
* [AMDGPU] Disassembler: Support for all VOP1 instructions.Nikolay Haustov2016-02-254-62/+492
| | | | | | | | | | | | | | | Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 llvm-svn: 261878
* don't repeat names in documentation comments; NFCSanjay Patel2016-02-253-222/+157
| | | | llvm-svn: 261877
* AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . ↵Igor Breger2016-02-2510-117/+1536
| | | | | | | | Change memory operand parser handling. Differential Revision: http://reviews.llvm.org/D17564 llvm-svn: 261862
* [mips][microMIPS] Implement DINSU, DINSM, DINS instructionsHrvoje Varga2016-02-2512-13/+94
| | | | | | Differential Revision: http://reviews.llvm.org/D16181 llvm-svn: 261860
* [AMDGPU] Assembler: Simplify handling of optional operandsNikolay Haustov2016-02-253-75/+77
| | | | | | | | | | | | | | | | | | | | | | Resubmit with index problem fixed. Verified with valgrind. Prepare to support DPP encodings. For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands. However this means that when parsing instruction which has no mnemonic prefix, we cannot add both default values for VOP3 and for DPP optional operands to OperandVector - neither instructions would match. So add default values for optional operands to MCInst during conversion instead. Mark more operands as IsOptional = 1 in .td files. Do not add default values for optional operands to OperandVector in AMDGPUAsmParser. Add default values for optional operands during conversion using new helper addOptionalImmOperand. Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one. Separate cvtFlat and cvtFlatAtomic. Fix CNDMASK_B32 definition to have no modifiers. Review: http://reviews.llvm.org/D17445 llvm-svn: 261856
* [PM] Add the IR unit type to the pass manager's logging and make all ofChandler Carruth2016-02-253-112/+113
| | | | | | | | | | | | | | | | | the testing more more explicit. This will currently fail on platforms without support for getTypeName. While an assert failure seems too harsh, I'm hoping we're OK with the regression test failure, and I'd like to find out about what platforms actually exist in this state if there are any so we can get implementations in place for them. But if we just can't fix all the host compilers to have a reasonably portable variant of getTypeName and are worried about xfailing this test on those platforms, I can add the horrible regular expression magic to make the tests support "unknown" here as well. llvm-svn: 261853
* [X86][SSE3] Added combine support for MOVDDUP/MOVSHDUP/MOVSLDUP target shufflesSimon Pilgrim2016-02-252-12/+9
| | | | | | Now that PerformShuffleCombine can handle unary shuffles. llvm-svn: 261843
* Revert r260064, "Disable llvm/test/tools/llvm-profdata/value-prof.proftext ↵NAKAMURA Takumi2016-02-251-2/+0
| | | | | | | | on win32 for now. Investigating." It seems unreproducible any more for me. llvm-svn: 261842
* Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands"NAKAMURA Takumi2016-02-253-79/+75
| | | | | | It brought undefined behavior. llvm-svn: 261839
* PM: Implement a basic loop pass managerJustin Bogner2016-02-2512-4/+757
| | | | | | | | | | | This creates the new-style LoopPassManager and wires it up with dummy and print passes. This version doesn't support modifying the loop nest at all. It will be far easier to discuss and evaluate the approaches to that with this in place so that the boilerplate is out of the way. llvm-svn: 261831
* Optimized loading (zextload) of i1 value from memory.Elena Demikhovsky2016-02-257-43/+42
| | | | | | | | | | | This patch is a partial revert of https://llvm.org/svn/llvm-project/llvm/trunk@237793. Extra "and" causes performance degradation. We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits. Differential Revision: http://reviews.llvm.org/D17541 llvm-svn: 261828
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