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* Allow overlaps between virtreg and physreg live ranges.Jakob Stoklund Olesen2012-09-067-14/+70
| | | | | | | | | | | | | | | | | The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. llvm-svn: 163336
* Handle overlapping regunit intervals in LiveIntervals::addKillFlags().Jakob Stoklund Olesen2012-09-063-4/+46
| | | | | | | | | | | | | | | | | | We will soon allow virtual register live ranges to overlap regunit live ranges when the physreg is defined as a copy of the virtreg: %EAX = COPY %vreg5 FOO %vreg5 BAR %EAX<kill> There is no real interference since %vreg5 and %EAX have the same value where they overlap. This patch prevents addKillFlags from adding virtreg kill flags to FOO where the assigned physreg is overlapping the virtual register live range. llvm-svn: 163335
* Clear kill flags while computing live ranges.Jakob Stoklund Olesen2012-09-061-1/+5
| | | | | | | | | Kill flags are difficult to maintain, and liveness queries are better handled by live intervals. Kill flags are reinserted after register allocation by addKillFlags(). llvm-svn: 163334
* Dont cast away const needlessly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-063-3/+4
| | | | llvm-svn: 163324
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-063-2/+10
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-066-8/+131
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* BasicAA: Recognize cyclic NoAlias phisArnold Schwaighofer2012-09-062-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhances basic alias analysis to recognize phis whose first incoming values are NoAlias and whose other incoming values are just the phi node itself through some amount of recursion. Example: With this change basicaa reports that ptr_phi and ptr_phi2 do not alias each other. bb: ptr = ptr2 + 1 loop: ptr_phi = phi [bb, ptr], [loop, ptr_plus_one] ptr2_phi = phi [bb, ptr2], [loop, ptr2_plus_one] ... ptr_plus_one = gep ptr_phi, 1 ptr2_plus_one = gep ptr2_phi, 1 This enables the elimination of one load in code like the following: extern int foo; int test_noalias(int *ptr, int num, int* coeff) { int *ptr2 = ptr; int result = (*ptr++) * (*coeff--); while (num--) { *ptr2++ = *ptr; result += (*coeff--) * (*ptr++); } *ptr = foo; return result; } Part 2/2 of fix for PR13564. llvm-svn: 163319
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-062-2/+79
| | | | | | Patch by Chris Lidbury. llvm-svn: 163318
* BasicAA: GEPs of NoAlias'ing base ptr with equivalent indices are NoAliasArnold Schwaighofer2012-09-062-9/+119
| | | | | | | | | | | | If we can show that the base pointers of two GEPs don't alias each other using precise analysis and the indices and base offset are equal then the two GEPs also don't alias each other. This is primarily needed for the follow up patch that analyses NoAlias'ing PHI nodes. Part 1/2 of fix for PR13564. llvm-svn: 163317
* Disable stack coloring by default in order to resolve the i386 failures.Nadav Rotem2012-09-062-3/+3
| | | | llvm-svn: 163316
* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-065-56/+53
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. llvm-svn: 163315
* AVX2 optimization.Elena Demikhovsky2012-09-062-0/+51
| | | | | | Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible. llvm-svn: 163312
* Fix a few old-GCC warnings. No functional change.Nadav Rotem2012-09-062-2/+2
| | | | llvm-svn: 163309
* Fix the test by specifying an exact cpu model.Nadav Rotem2012-09-061-2/+2
| | | | llvm-svn: 163307
* Fix self-host; ensure signedness is consistent.James Molloy2012-09-061-2/+2
| | | | llvm-svn: 163306
* Fix switch_to_lookup_table.ll test from r163302.Hans Wennborg2012-09-062-11/+12
| | | | | | | | The lookup tables did not get built in a deterministic order. This makes them get built in the order that the corresponding phi nodes were found. llvm-svn: 163305
* Improve codegen for BUILD_VECTORs on ARM.James Molloy2012-09-062-10/+90
| | | | | | If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base. llvm-svn: 163304
* Build lookup tables for switches (PR884)Hans Wennborg2012-09-063-2/+429
| | | | | | | | | | | | | | | | | | | | | | This adds a transformation to SimplifyCFG that attemps to turn switch instructions into loads from lookup tables. It works on switches that are only used to initialize one or more phi nodes in a common successor basic block, for example: int f(int x) { switch (x) { case 0: return 5; case 1: return 4; case 2: return -2; case 5: return 7; case 6: return 9; default: return 42; } This speeds up the code by removing the hard-to-predict jump, and reduces code size by removing the code for the jump targets. llvm-svn: 163302
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-0622-16/+1057
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate ↵James Molloy2012-09-064-18/+102
| | | | | | to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. llvm-svn: 163298
* Remove duplicated helper functionMichael Liao2012-09-061-17/+1
| | | | llvm-svn: 163295
* Use iPTR instead of i32 for extract_subvector/insert_subvector index in ↵Craig Topper2012-09-062-78/+78
| | | | | | lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. llvm-svn: 163293
* Add patterns for converting stores of subvector_extracts of lower 128-bits ↵Craig Topper2012-09-062-9/+91
| | | | | | of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. llvm-svn: 163292
* Revert "Enable MCJIT tests on Darwin."Jim Grosbach2012-09-061-1/+1
| | | | | | | | This reverts commit 163278. Works OK on x86_64, but not i386. Will re-enable when that's cleared up. llvm-svn: 163290
* Whitespace.NAKAMURA Takumi2012-09-061-2/+2
| | | | llvm-svn: 163289
* Unix/Signals.inc: Fix a typo. Thanks to Dani Berg!NAKAMURA Takumi2012-09-061-1/+1
| | | | llvm-svn: 163288
* There are some Mips instructions that are lowered by the Jack Carter2012-09-066-95/+124
| | | | | | | | | | | | | | | | assembler such as shifts greater than 32. In the case of direct object, the code gen needs to do this lowering since the assembler is not involved. With the advent of the llvm-mc assembler, it also needs to do the same lowering. This patch makes that specific lowering code accessible to both the direct object output and the assembler. This patch does not affect generated output. llvm-svn: 163287
* Update function names to conform to guidelines.Jim Grosbach2012-09-061-26/+26
| | | | | | No functional change. llvm-svn: 163279
* Enable MCJIT tests on Darwin.Jim Grosbach2012-09-061-1/+1
| | | | llvm-svn: 163278
* Mips specific llvm assembler support for branch and jump instructions.Jack Carter2012-09-062-2/+73
| | | | | | | Test case included. Contributer: Vladimir Medic llvm-svn: 163277
* Don't include stdint.h directly.Eli Friedman2012-09-061-1/+1
| | | | llvm-svn: 163276
* Remove predicated pseudo-instructions.Jakob Stoklund Olesen2012-09-052-100/+0
| | | | | | | These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. llvm-svn: 163275
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-054-66/+41
| | | | | | | | | | | | | | | | | | | | Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
* [ms-inline asm] Use the asm dialect from the MI to set the parser dialect.Chad Rosier2012-09-052-3/+7
| | | | llvm-svn: 163273
* Add missing file for test.Nick Lewycky2012-09-051-0/+0
| | | | llvm-svn: 163272
* Teach libObject about some more ELF relocations. llvm-objdump -r now knowsNick Lewycky2012-09-052-6/+30
| | | | | | every relocation in C++ hello world built with debug info. llvm-svn: 163271
* JumpThreading: when default destination is the destination of some cases in aManman Ren2012-09-052-3/+42
| | | | | | | | | switch, make sure we include the value for the cases when calculating edge value from switch to the default destination. rdar://12241132 llvm-svn: 163270
* Mips specific llvm assembler support for ALU instructions. This includesJack Carter2012-09-052-22/+448
| | | | | | | register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
* Cleanup a few magic numbers.Chad Rosier2012-09-053-3/+3
| | | | llvm-svn: 163263
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-0517-21/+21
| | | | llvm-svn: 163258
* [ms-inline asm] We only need one bit to represent the AsmDialect in theChad Rosier2012-09-053-13/+6
| | | | | | MachineInstr. llvm-svn: 163257
* Constify this properly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-051-4/+4
| | | | llvm-svn: 163256
* Mark checkSignature const, and in turn stop casting away const fromRoman Divacky2012-09-052-3/+3
| | | | | | ArchiveMemberHeader. Found by gcc48 -Wcast-qual. llvm-svn: 163255
* Constify SDNodeIterator an stop its only non-const user being cast strippedRoman Divacky2012-09-052-5/+5
| | | | | | of its constness. Found by gcc48 -Wcast-qual. llvm-svn: 163254
* Constify subtarget info properly so that we dont cast away the const inRoman Divacky2012-09-055-11/+11
| | | | | | the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. llvm-svn: 163251
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-053-13/+13
| | | | | | by casting. Found with gcc48. llvm-svn: 163247
* [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.Chad Rosier2012-09-054-3/+25
| | | | llvm-svn: 163243
* Fix a bug.Jan Wen Voung2012-09-051-1/+1
| | | | llvm-svn: 163242
* revert the additional stuff.Jan Wen Voung2012-09-051-6/+4
| | | | llvm-svn: 163241
* Clean up llvm-bcanalyzer to print to consistent streams.Jan Wen Voung2012-09-051-13/+17
| | | | | | | | Avoid interleaving fprintf(stderr,...) and outs() << ...; Also add a column to show "bytes-per" for each record. llvm-svn: 163240
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