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* Minor format change and fixing typos in the comments. NFC.Rong Xu2016-04-281-10/+7
| | | | llvm-svn: 267905
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-284-0/+53
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [mips][atomics] Fix partword atomic binary operation implementationSimon Dardis2016-04-284-73/+105
| | | | | | | | | | | | | | | Currently Mips::emitAtomicBinaryPartword() does not properly respect the width of pointers. For MIPS64 this causes the memory address that the ll/sc sequence uses to be truncated. At runtime this causes a segmentation fault. This can be fixed by applying similar changes as r266204, so that a full 64bit pointer is loaded. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19651 llvm-svn: 267900
* [SLPVectorizer] Extend SLP Vectorizer to deal with aggregates.Arch D. Robison2016-04-282-37/+340
| | | | | | | | The refactoring portion part was done as r267748. http://reviews.llvm.org/D14185 llvm-svn: 267899
* [GVN] Minor code cleanup. NFC.Chad Rosier2016-04-282-74/+68
| | | | | | | Differential Revision: http://reviews.llvm.org/D18828 Patch by Aditya Kumar! llvm-svn: 267898
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-284-3/+54
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* Debug Info: Restore the pre-r240853 behavior for DWARF2 bitfields.Adrian Prantl2016-04-282-25/+11
| | | | | | | | | The DWARF2 specification of DW_AT_bit_offset is ambiguous for little-endian machines, but by restoring to the old behavior we match what debuggers expect and what other popular compilers generate. llvm-svn: 267896
* Debug info: Support DWARF4 bitfields via DW_AT_data_bit_offset.Adrian Prantl2016-04-283-28/+154
| | | | | | | | | | | | | The DWARF2 specification of DW_AT_bit_offset was written from the perspective of a big-endian machine with unclear semantics for other systems. DWARF4 deprecated DW_AT_bit_offset and introduced a new attribute DW_AT_data_bit_offset that simply counts the number of bits from the beginning of the containing entity regardless of endianness. After this patch LLVM emits DW_AT_bit_offset for DWARF 2 or 3 and DW_AT_data_bit_offset when DWARF 4 or later is requested. llvm-svn: 267895
* [EarlyCSE] Change LoadValue field Value *Data to Instruction *Inst. NFC.Geoff Berry2016-04-281-9/+9
| | | | | | Made in preparation for adding MemorySSA support to EarlyCSE. llvm-svn: 267893
* [libFuzzer] Improve documentationKostya Serebryany2016-04-281-155/+390
| | | | | | | | | | Reviewers: kcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19585 llvm-svn: 267892
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-282-1/+61
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [EarlyCSE] Sort includes. NFC.Geoff Berry2016-04-281-1/+1
| | | | | | | | | | Reviewers: mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19617 llvm-svn: 267890
* Rangify for loops, NFC.Yaron Keren2016-04-281-22/+14
| | | | llvm-svn: 267889
* [Inliner] Formatting. NFC.Chad Rosier2016-04-281-36/+41
| | | | | | | Patch by Aditya Kumar! Differential Revision: http://reviews.llvm.org/D19047 llvm-svn: 267888
* [InstCombine] Remove trailing whitespace. NFC.Ahmed Bougacha2016-04-281-1/+1
| | | | | | r267873. llvm-svn: 267887
* [InstCombine][SSE] Add MOVMSK support to SimplifyDemandedUseBitsSimon Pilgrim2016-04-282-27/+32
| | | | | | | | | | The MOVMSK instructions copies a vector elements' sign bits to the low bits of a scalar register and zeros the high bits. This patch adds MOVMSK support to SimplifyDemandedUseBits so that its aware that the upper bits are known to be zero. It also removes the call to MOVMSK if none of the lower bits are actually required and just returns zero. Differential Revision: http://reviews.llvm.org/D19614 llvm-svn: 267873
* [X86] Remove unused operand from a function and all its callers. NFCCraig Topper2016-04-285-10/+8
| | | | llvm-svn: 267854
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-2815-85/+14
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* CodeGen: Add DetectDeadLanes pass.Matthias Braun2016-04-287-0/+946
| | | | | | | | | | | | | | | | | | | | The DetectDeadLanes pass performs a dataflow analysis of used/defined subregister lanes across COPY instructions and instructions that will get lowered to copies. It detects dead definitions and uses reading undefined values which are obscured by COPY and subregister usage. These dead definitions cause trouble in the register coalescer which cannot deal with definitions suddenly becoming dead after coalescing COPY instructions. For now the pass only adds dead and undef flags to machine operands. It should be possible to extend it in the future to remove the dead instructions and redo the analysis for the affected virtual registers. Differential Revision: http://reviews.llvm.org/D18427 llvm-svn: 267851
* TableGen: Produce CoveredBySubRegs summary for register classesMatthias Braun2016-04-284-3/+12
| | | | | | This will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267850
* TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()Matthias Braun2016-04-282-12/+48
| | | | | | | | | This function performs the reverse computation of composeSubRegIndexLaneMask(). It will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267849
* TableGen: Support lanemasks for classes without subregistersMatthias Braun2016-04-282-39/+51
| | | | | | | | | | | | | Previously using lanemasks on registers without any subregisters was not well defined. This commit extends TargetRegisterInfo/tablegen to: - Report a lanemask of 1 for regclasses without subregisters - Do the right thing when mapping a 0/1 lanemask from a class without subregisters into a class with subregisters in TargetRegisterInfo::composeSubRegIndexLaneMasks(). This will be used in the upcoming "DetectDeadLanes" patch. llvm-svn: 267848
* LiveIntervalAnalysis: Fix handleMove() using wrong value numbersMatthias Braun2016-04-281-2/+1
| | | | | | | | | | handleMove() was incorrectly swapping two value numbers. This was missed before because the problem only occured when moving subregister definitions and needed -verify-machineinstrs to be detected. I cannot add a testcase as long as I cannot reapply r260905/r260806. llvm-svn: 267840
* [AArch64] Expand CTTZ for all vector types.Craig Topper2016-04-281-0/+9
| | | | llvm-svn: 267837
* Fix bogus documentation for StringRef::slice in the End < Start case.Richard Smith2016-04-281-3/+4
| | | | llvm-svn: 267831
* Use llvm:Twine instead of std::to_string.Chaoren Lin2016-04-283-11/+11
| | | | | | | | | | | | std::to_string is not available from the Android NDK. Reviewers: lhames, ovyalov, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19638 llvm-svn: 267829
* Update test to use FileCheckSanjay Patel2016-04-281-14/+41
| | | | | | Also, add some metadata to show what that currently looks like. llvm-svn: 267827
* [SystemZ] Support Swift Calling ConventionBryan Chan2016-04-287-3/+658
| | | | | | | | | | | | | | | | Summary: Port rL265480, rL264754, rL265997 and rL266252 to SystemZ, in order to enable the Swift port on the architecture. SwiftSelf and SwiftError are assigned to R10 and R9, respectively, which are normally callee-saved registers. For more information, see: RFC: Implementing the Swift calling convention in LLVM and Clang https://groups.google.com/forum/#!topic/llvm-dev/epDd2w93kZ0 Reviewers: kbarton, manmanren, rjmccall, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19414 llvm-svn: 267823
* LTO: Don't bother trying to mangle unnamed globals, as they can't be ↵Peter Collingbourne2016-04-272-0/+14
| | | | | | | | | | | | | | preserved with MustPreserveSymbols. Summary: Should fix sanitizer-windows bot. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19635 llvm-svn: 267820
* Fix bugs in llvm-objdump printing the last word for -section in non i386 and ↵Kevin Enderby2016-04-273-3/+7
| | | | | | | | | | | x86 files. Two problems, 1) for the last 4 bytes it would print them as separate bytes not a word and 2) it would print the same last byte for those bytes less than a word. rdar://25938224 llvm-svn: 267819
* Parse module information from DBI stream.Zachary Turner2016-04-277-2/+275
| | | | | | | | | | | | This gets more data out of the DBI strema of the PDB. In particular it extracts the metadata for the list of modules (compilands) that this PDB contains info about, and adds support for dumping these fields to llvm-pdbdump. Differential Revision: http://reviews.llvm.org/D19570 Reviewed By: ruiu llvm-svn: 267818
* [ImplicitNullChecks] Properly update the live-in of the block of the memory ↵Quentin Colombet2016-04-271-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | operation. We basically replace: HoistBB: cond_br NullBB, NotNullBB NullBB: ... NotNullBB: <reg> = load into HoistBB <reg> = load_faulting_op NullBB uncond_br NotNullBB NullBB: ... NotNullBB: ## <reg> is now live-in of NotNullBB ... This partially fixes the machine verifier error for test/CodeGen/X86/implicit-null-check.ll, but it still fails because of the implicit CFG structure. llvm-svn: 267817
* more buildbot failure fix to r267792Rong Xu2016-04-271-1/+1
| | | | | | __llvm_prf_nm length is embedded in llvm_used. Relax llvm_used check. llvm-svn: 267816
* [PGO] Promote indirect calls to conditional direct calls with value-profileRong Xu2016-04-2713-1/+1092
| | | | | | | | | | This patch implements the transformation that promotes indirect calls to conditional direct calls when the indirect-call value profile meta-data is available. Differential Revision: http://reviews.llvm.org/D17864 llvm-svn: 267815
* [SimplifyCFG] propagate branch metadata when creating selectSanjay Patel2016-04-271-2/+2
| | | | | | | | There's no existing test for this path, and I don't know how to expose it in a regression test, but I'm assuming there's some reason this path exists. llvm-svn: 267813
* [RuntimeDyld] Propagate another dropped error in RuntimeDyldELF.Lang Hames2016-04-271-1/+2
| | | | | | This should fix the PPC64 bots. llvm-svn: 267810
* [X86] Enable the post-RA-scheduler for clang's default 32-bit cpu.Mitch Bodart2016-04-273-12/+76
| | | | | | | | | For compilations with no explicit cpu specified, this exhibits nice gains on Silvermont, with neutral performance on big cores. Differential Revision: http://reviews.llvm.org/D19138 llvm-svn: 267809
* Fix a bug in llvm-objdump printing of 32-bit addresses for -section in non ↵Kevin Enderby2016-04-273-1/+5
| | | | | | | | i386 and x86 files. rdar://25896202 llvm-svn: 267807
* [X86][FastISel] Make sure we use the right register class when we select stores.Quentin Colombet2016-04-272-4/+12
| | | | llvm-svn: 267806
* Fix buildbot failure due to r267792Rong Xu2016-04-271-1/+1
| | | | | | Relax the test check as some targets do not have name compression. llvm-svn: 267803
* [Hexagon] Merging nops in to previous packet rather than always creating a ↵Colin LeMahieu2016-04-272-17/+129
| | | | | | new one. llvm-svn: 267798
* [X86] Fix the lowering of TLS calls.Quentin Colombet2016-04-274-10/+18
| | | | | | | | | | | The callseq_end node must be glued with the TLS calls, otherwise, the generic code will miss the uses of the returned value and will mark it dead. Moreover, TLSCall 64-bit pseudo must not set an implicit-use on RDI, the pseudo uses the symbol address at this point not RDI and the lowering will do the right thing. llvm-svn: 267797
* [MCAssembler] Allow backend to finalize layout post-relaxation.Colin LeMahieu2016-04-272-0/+5
| | | | | | Differential revision: http://reviews.llvm.org/D19429 llvm-svn: 267796
* [PGO] Prohibit address recording if the function is both internal and COMDATRong Xu2016-04-272-0/+30
| | | | | | Differential Revision: http://reviews.llvm.org/D19515 llvm-svn: 267792
* AMDGPU: Account for globals in AMDGPUPromoteAlloca passMatt Arsenault2016-04-272-2/+36
| | | | | | Patch by Bas Nieuwenhuizen llvm-svn: 267791
* [RuntimeDyld] Add missing include - <string> is requried for std::to_string.Lang Hames2016-04-273-0/+3
| | | | | | | This should fix the compile error that showed up in build: http://lab.llvm.org:8011/builders/lldb-x86_64-ubuntu-14.04-buildserver/builds/6754/ llvm-svn: 267790
* [RuntimeDyld] Propagate Errors from findPPC64TOCSection.Lang Hames2016-04-271-3/+6
| | | | llvm-svn: 267789
* Add a test case for the crash fixed with r267037. David Blaikie said it ↵Kevin Enderby2016-04-272-0/+3
| | | | | | | | | would be nice to have! This was crashing llvm-objdump with -macho -objc-meta-data when trying dump a non-existent section. So the test binary is simply created from an empty .s file compiled with: clang -arch armv7 empty.s -c llvm-svn: 267782
* [ARM] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.Ahmed Bougacha2016-04-271-2/+2
| | | | | | | | | We run after PEI. Found via inspection; no obvious testcase. Follow-up to r266679. llvm-svn: 267781
* [AArch64] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.Ahmed Bougacha2016-04-271-2/+2
| | | | | | | | | We run after PEI. Found via inspection; no obvious testcase. Follow-up to r266339. llvm-svn: 267780
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