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* Convert two std::vectors to SmallVectors for a 3.4% speedup running -scalarreplCameron Zwarich2011-01-231-2/+2
| | | | | | on test-suite + SPEC2000 & SPEC2006. llvm-svn: 124068
* have AllocaInfo store the alloca being inspected, simplifying callers.Chris Lattner2011-01-231-22/+24
| | | | | | No functionality change. llvm-svn: 124067
* Rearrange some code a bit. Change MarkUnsafe to Chris Lattner2011-01-231-27/+29
| | | | | | | | handle the "Transformation preventing inst" printing, so that -scalarrepl -debug will always print the rejected instruction. No functionality change. llvm-svn: 124066
* Convert a std::vector to a SmallVector for another 5.4% speedup on domtree.Cameron Zwarich2011-01-231-2/+2
| | | | llvm-svn: 124065
* remove an old hack that avoided creating MMX datatypes. TheChris Lattner2011-01-232-26/+3
| | | | | | X86 backend has been fixed. llvm-svn: 124064
* Use value ranges to fold ext(trunc) in SCEV when possible.Nick Lewycky2011-01-232-0/+68
| | | | llvm-svn: 124062
* In the simpler version of the link-eval data structure that we use in dominatorCameron Zwarich2011-01-232-38/+23
| | | | | | | | | | | | | computation, the Ancestor field is always set to the Parent, so we can remove the explicit link entirely and merge the Parent and Ancestor fields. Instead of checking for whether an ancestor exists for a node or not, we simply check whether the node has already been processed. This is simpler if Compress is inlined into Eval, so I did that as well. This is about a 3% speedup running -domtree on test-suite + SPEC2000 & SPEC2006, but it also opens up some opportunities for further improvement. llvm-svn: 124061
* Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola2011-01-238-26/+51
| | | | | | Add support for SHT_X86_64_UNWIND. llvm-svn: 124059
* Remove useless struct fields.Cameron Zwarich2011-01-232-10/+2
| | | | llvm-svn: 124058
* Remove friend declaration for removed function.Cameron Zwarich2011-01-231-5/+0
| | | | llvm-svn: 124057
* Remove more duplicated code.Rafael Espindola2011-01-2312-165/+158
| | | | llvm-svn: 124056
* Convert a std::vector to a SmallVector.Cameron Zwarich2011-01-231-1/+1
| | | | llvm-svn: 124055
* Remove duplicated code.Rafael Espindola2011-01-2312-152/+90
| | | | llvm-svn: 124054
* Simplify some code now that we've removed the more optimal (but slower) versionCameron Zwarich2011-01-231-8/+2
| | | | | | of the link-eval data structure from dominator computation. llvm-svn: 124053
* Have SCEV turn sext(x) into zext(x) when x is s>= 0. This applies many times inNick Lewycky2011-01-221-0/+4
| | | | | | "make check" alone. llvm-svn: 124046
* Add a FIXME explaining the move to a single indirect call bonus per functionEric Christopher2011-01-221-0/+5
| | | | | | that we can change from indirect to direct. llvm-svn: 124045
* Only apply the devirtualization bonus once instead of per-call site in theEric Christopher2011-01-221-2/+6
| | | | | | | | target function. Fixes part of rdar://8546196 llvm-svn: 124044
* Pass sret arguments through the stack instead of through registers in Sparc ↵Venkatraman Govindaraju2011-01-224-4/+111
| | | | | | backend. It makes the code generated more compliant with the sparc32 ABI. llvm-svn: 124030
* Remove dead ivar.Benjamin Kramer2011-01-221-4/+0
| | | | llvm-svn: 124028
* Added ICC, FCC as uses of movcc instruction to generate correct code when ↵Venkatraman Govindaraju2011-01-222-64/+102
| | | | | | -mattr=v9 is used. llvm-svn: 124027
* ARM uses '.' in their tokens. Give it a name instead of a numeric value.Bill Wendling2011-01-221-0/+1
| | | | llvm-svn: 124026
* add DW_TAG for rvalue refs.Chris Lattner2011-01-221-0/+1
| | | | llvm-svn: 124019
* Actually check memcpy lengths, instead of just commenting aboutDan Gohman2011-01-212-2/+32
| | | | | | how they should be checked. llvm-svn: 123999
* Sparc backend: Venkatraman Govindaraju2011-01-214-39/+62
| | | | | | | Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. llvm-svn: 123997
* Just because we have determined that an (fcmp | fcmp) is true for A < B,Owen Anderson2011-01-212-3/+29
| | | | | | | A == B, and A > B, does not mean we can fold it to true. We still need to check for A ? B (A unordered B). llvm-svn: 123993
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-2115-114/+201
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Clang was not parsing target triples involving EABI and was generating wrong ↵Renato Golin2011-01-213-9/+53
| | | | | | IR (wrong PCS) and passing the wrong information down llc via the target-triple printed in IR. I've fixed this by adding the parsing of EABI into LLVM's Triple class and using it to choose the correct PCS in Clang's Tools. A Clang patch is on its way to use this infrastructure. llvm-svn: 123990
* Handles libffi on the CMake build.Oscar Fuentes2011-01-215-3/+58
| | | | | | Patch by arrowdodger! llvm-svn: 123976
* Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",Bruno Cardoso Lopes2011-01-214-15/+48
| | | | | | | qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975
* Implement support for byval arguments in Sparc backend.Venkatraman Govindaraju2011-01-212-1/+49
| | | | llvm-svn: 123974
* SCCP doesn't actually preserve the CFG. It will delete and insert terminatorNick Lewycky2011-01-211-4/+0
| | | | | | instructions. llvm-svn: 123973
* Revert "Object: Renable the tests now that none of the build bots complain ↵Michael J. Spencer2011-01-212-0/+0
| | | | | | | | about aliasing." This reverts commit 281f3901b7b0869929caf8946c1ad1228bc38922. llvm-svn: 123972
* Enable support for precise scheduling of the instruction selectionAndrew Trick2011-01-213-7/+12
| | | | | | | | | | | | | | | | | | | | | | | DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). llvm-svn: 123971
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-2110-63/+88
| | | | | | | | | | | flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
* fix PR9013, an infinite loop in instcombine.Chris Lattner2011-01-212-2/+27
| | | | llvm-svn: 123968
* update obsolete comment.Chris Lattner2011-01-211-4/+3
| | | | llvm-svn: 123965
* Object: Renable the tests now that none of the build bots complain about ↵Michael J. Spencer2011-01-212-0/+0
| | | | | | aliasing. llvm-svn: 123964
* Don't try to pull vector bitcasts that change the number of elements throughNick Lewycky2011-01-212-3/+28
| | | | | | | a select. A vector select is pairwise on each element so we'd need a new condition with the right number of elements to select on. Fixes PR8994. llvm-svn: 123963
* Object: Fix type punned pointer issues by making DataRefImpl a union and ↵Michael J. Spencer2011-01-213-84/+82
| | | | | | using intptr_t. llvm-svn: 123962
* tblgen: Add support for non-inheritable attributesPeter Collingbourne2011-01-211-12/+47
| | | | | | | This patch makes the necessary changes to TableGen to support non-inheritable attributes. llvm-svn: 123958
* Add a constant folding of casts from zero to zero. Fixes PR9011!Nick Lewycky2011-01-212-0/+39
| | | | | | | | While here, I'd like to complain about how vector is not an aggregate type according to llvm::Type::isAggregateType(), but they're listed under aggregate types in the LangRef and zero vectors are stored as ConstantAggregateZero. llvm-svn: 123956
* Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relativeEvan Cheng2011-01-202-7/+7
| | | | | | | | | value, the "add pc" must be CSE'ed at the same time. We could follow the same approach as T2 by adding pseudo instructions that combine the ldr + "add pc". But the better approach is to use movw + movt (which I will enable soon), so I'll leave this as a TODO. llvm-svn: 123949
* Implement requiredTransitiveTobias Grosser2011-01-202-1/+56
| | | | | | | The PassManager did not implement the transitivity of requiredTransitive. This was unnoticed since 2006. llvm-svn: 123942
* RegionPassPrinter should contain the name of the pass printedTobias Grosser2011-01-201-2/+2
| | | | llvm-svn: 123941
* Add testcases for clz encodingBruno Cardoso Lopes2011-01-202-0/+6
| | | | llvm-svn: 123937
* Fix the encoding and parsing of clrex instructionBruno Cardoso Lopes2011-01-204-5/+13
| | | | llvm-svn: 123936
* Move InstAlias check of argument types to a separate loop.Bob Wilson2011-01-201-11/+14
| | | | llvm-svn: 123934
* Tidy comment.Bob Wilson2011-01-201-2/+2
| | | | llvm-svn: 123933
* Fix broken check for InstAlias argument used with different types.Bob Wilson2011-01-201-0/+1
| | | | llvm-svn: 123932
* Precompute InstAlias operand mapping to result instruction operand indices.Bob Wilson2011-01-203-24/+9
| | | | | | | There should be no functional change from this, but I think it's simpler this way. llvm-svn: 123931
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