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* Add missing ELF constants.Michael J. Spencer2011-10-131-18/+216
| | | | llvm-svn: 141840
* Also inflate register classes around inline asm.Jakob Stoklund Olesen2011-10-122-4/+28
| | | | | | | | | | Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. llvm-svn: 141836
* Add MachineInstr::getRegClassConstraint().Jakob Stoklund Olesen2011-10-122-0/+46
| | | | | | | | | Most instructions have some requirements for their register operands. Usually, this is expressed as register class constraints in the MCInstrDesc, but for inline assembly the constraints are encoded in the flag words. llvm-svn: 141835
* Extract a method for finding the inline asm flag operand.Jakob Stoklund Olesen2011-10-122-30/+50
| | | | llvm-svn: 141834
* Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen2011-10-123-8/+58
| | | | | | | | | | | | | The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. llvm-svn: 141833
* Attempt to fix MSVC build.Eli Friedman2011-10-121-2/+2
| | | | llvm-svn: 141831
* We need to verify that the machine instruction we're using as a replacement forBill Wendling2011-10-122-0/+127
| | | | | | | | | | our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> llvm-svn: 141830
* Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman2011-10-121-1/+1
| | | | | | behavior. Based on patch by Ahmed Charles. llvm-svn: 141829
* The VMAs stored in the symbol table of a MachO file are absolute addresses, ↵Owen Anderson2011-10-121-9/+9
| | | | | | not offsets from the section. llvm-svn: 141828
* Use unsigned multiply to hash integers, so we don't end up with undefined ↵Eli Friedman2011-10-121-5/+5
| | | | | | behavior for large signed integers. Based on patch by Ahmed Charles. llvm-svn: 141827
* Removed colons from some target datalayout strings in test, since they don't ↵Lang Hames2011-10-1217-17/+17
| | | | | | match the required format. llvm-svn: 141825
* Don't label a STAB debugging symbol as a function symbol.Owen Anderson2011-10-121-0/+5
| | | | llvm-svn: 141824
* sectionContainsSymbol needs to be based on VMA's rather than section indices ↵Owen Anderson2011-10-121-2/+17
| | | | | | to properly account for files with segment load commands that contain no sections. llvm-svn: 141822
* Fix a couple hash functions so that they do not depend on undefined shifts. ↵Eli Friedman2011-10-121-2/+2
| | | | | | Based on patch by Ahmed Charles. llvm-svn: 141820
* ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach2011-10-121-14/+17
| | | | | | | The disassembler needs to use the AM5 factory methods instead of just building up the immediate directly. llvm-svn: 141819
* Fix APFloat::getSmallestNormalized so the shift doesn't depend on undefined ↵Eli Friedman2011-10-121-1/+1
| | | | | | behavior. Patch from Ahmed Charles. llvm-svn: 141818
* Fix APFloat::getLargest so that it actually returns the correct value. ↵Eli Friedman2011-10-122-2/+8
| | | | | | Found by accident while reviewing a patch to nearby code. llvm-svn: 141816
* Section indices in MachO symbol tables begin at 1, not 0.Owen Anderson2011-10-121-1/+1
| | | | llvm-svn: 141815
* Finish supporting cpp #file/line comments in assembler for error messages. SoKevin Enderby2011-10-123-7/+75
| | | | | | | | for cpp pre-processed assembly we give correct filename and line numbers when reporting errors in assembly files when using clang and -integrated-as on .s files. rdar://8998895 llvm-svn: 141814
* Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng2011-10-121-6/+15
| | | | | | to investigate the regressions. llvm-svn: 141813
* To find the exiting VN of a LiveInterval from a block, use the previous slotCameron Zwarich2011-10-121-1/+1
| | | | | | | | | | | rather than the previous index. If a block has a single instruction, the previous index may be in a different basic block. I have no clue how this used to work on all of test-suite, because now this failure is seen quite often when trying to compile code with -strong-phi-elim. This fixes PR10252. llvm-svn: 141812
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-125-100/+237
| | | | llvm-svn: 141811
* Hoist vector.size() computation out of the loop. No functionality change.Nick Lewycky2011-10-121-1/+2
| | | | llvm-svn: 141807
* addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach2011-10-121-24/+0
| | | | llvm-svn: 141794
* ARM encoding tests for STC.Jim Grosbach2011-10-121-0/+85
| | | | llvm-svn: 141787
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-127-9/+99
| | | | llvm-svn: 141786
* 80 columns.Jim Grosbach2011-10-121-2/+1
| | | | llvm-svn: 141781
* Tidy up. Formatting.Jim Grosbach2011-10-121-2/+2
| | | | llvm-svn: 141780
* Fix a thinko that Nick noticed. The previous code actually worked asDan Gohman2011-10-121-1/+1
| | | | | | intended, but only by accident. llvm-svn: 141779
* lib/Object/ELFObjectFile.cpp: Fix undefined behavior for ↵NAKAMURA Takumi2011-10-121-1/+4
| | | | | | | | MC/ELF/many-section.s not to fail (on msvc). DenseMap::lookup(k) would return "default constructor value" when k was not met. It would be useless when value type were POD. llvm-svn: 141774
* Expand the check for a landing pad so that it looks at the basic block'sBill Wendling2011-10-121-5/+11
| | | | | | | containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. llvm-svn: 141767
* Use an existing function.Jakob Stoklund Olesen2011-10-121-10/+2
| | | | llvm-svn: 141763
* Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.Akira Hatanaka2011-10-122-13/+5
| | | | llvm-svn: 141761
* Fix encoding of 32-bit integer instructions. Change names of operands and nodes.Akira Hatanaka2011-10-121-87/+108
| | | | | | Remove unused classes. llvm-svn: 141757
* Make this use a public accessor too.Eric Christopher2011-10-121-1/+1
| | | | llvm-svn: 141752
* Add missing space.Nick Lewycky2011-10-121-1/+1
| | | | llvm-svn: 141750
* Fix indent in comment.Nick Lewycky2011-10-121-1/+1
| | | | llvm-svn: 141749
* Fix r141744.Evan Cheng2011-10-121-1/+19
| | | | | | | | | 1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. llvm-svn: 141747
* Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen2011-10-122-3/+64
| | | | | | | | | | | | | | | | | | | | | | When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. llvm-svn: 141746
* Refine r141689 with a tri-state variable.Evan Cheng2011-10-111-19/+23
| | | | | | Also teach MachineLICM to avoid "speculation" when register pressure is high. llvm-svn: 141744
* Change name of class to ArithOverflowR.Akira Hatanaka2011-10-111-3/+3
| | | | llvm-svn: 141743
* Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logicalAkira Hatanaka2011-10-112-35/+19
| | | | | | instructions with two register operands derive from it. llvm-svn: 141742
* Make this test more specific. There are 3 stats that matched "machine-licm".Bob Wilson2011-10-111-1/+1
| | | | llvm-svn: 141741
* Use public accessors on the scope that is returned.Eric Christopher2011-10-111-2/+2
| | | | llvm-svn: 141739
* Fix comment.Akira Hatanaka2011-10-111-1/+1
| | | | llvm-svn: 141737
* Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bitAkira Hatanaka2011-10-112-43/+25
| | | | | | | arithmetic and logical instructions with three register operands derive from them. Fix instruction encoding too. llvm-svn: 141736
* target data is a contract with the code generator, not the "processor"Chris Lattner2011-10-111-1/+1
| | | | llvm-svn: 141734
* improve some of the documentation around target data layout strings.Chris Lattner2011-10-112-0/+23
| | | | llvm-svn: 141733
* Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher2011-10-1110-10/+115
| | | | | | | | | | | | | file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 llvm-svn: 141729
* Formatting.Eric Christopher2011-10-111-2/+1
| | | | llvm-svn: 141728
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