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* R600: Allow ftruncTom Stellard2013-12-203-0/+18
| | | | | | | | | | | v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc v3: move ftrunc pattern next to TRUNC definition, it's available since R600 Patch By: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 197783
* Remove extra check line that's failing on windows and not necessary atEric Christopher2013-12-201-1/+0
| | | | | | the moment. llvm-svn: 197782
* This test requires object emission.Eric Christopher2013-12-201-0/+1
| | | | llvm-svn: 197781
* Ranges in the .debug_range section need to have begin and end labels,Eric Christopher2013-12-201-13/+8
| | | | | | assert that this is so. llvm-svn: 197780
* Makefile.unittest: cleanup may fail. Add '-' in the action.NAKAMURA Takumi2013-12-201-1/+1
| | | | llvm-svn: 197777
* Add support for a CU to output a set of ranges for the CU. This is usefulEric Christopher2013-12-203-20/+124
| | | | | | | | when you want to have the full list of addresses for a particular CU or when you have multiple modules linked together and can't depend upon the ordering of a single CU for begin/end ranges. llvm-svn: 197776
* Remove the AnyPointerSize and AnyEndianness enumerators, which were left fromDmitri Gribenko2013-12-201-2/+2
| | | | | | LLVM's early days. Today LLVM IR is always target-specific. llvm-svn: 197772
* When parsing data layout string looking for endianness, use the correct defaultDmitri Gribenko2013-12-201-1/+1
| | | | llvm-svn: 197771
* Correctly apply the default pointer sizeDmitri Gribenko2013-12-201-1/+1
| | | | llvm-svn: 197770
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-2011-137/+138
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* move test back into the parent directory and add a REQUIRES: obj emission.Adrian Prantl2013-12-201-4/+1
| | | | llvm-svn: 197759
* Makefile.ocaml: Tweak to use --system-libs.NAKAMURA Takumi2013-12-201-1/+1
| | | | llvm-svn: 197758
* Fix documentation typosAlp Toker2013-12-2010-14/+14
| | | | llvm-svn: 197757
* Update the ML test to expect the new string format of getStringRepresentation.Rafael Espindola2013-12-191-3/+1
| | | | llvm-svn: 197750
* Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me withKevin Enderby2013-12-192-2/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this commit as the only one on the Blamelist so I quickly reverted this. However it was actually Nick's change who has since fixed that issue. Original commit message: Changed the X86 assembler for intel syntax to work with directional labels. The X86 assembler as a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following an Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197744
* Use $ORIGIN when setting rpath.Rafael Espindola2013-12-191-0/+2
| | | | | | | | | | This matches what the configure build does. Patch by Jan Vesely. Fixes pr14189. llvm-svn: 197743
* Change getStringRepresentation to skip defaults.Rafael Espindola2013-12-191-17/+45
| | | | | | | | | | I have a pending change for clang to use getStringRepresentation to check that its DataLayout is in sync with llvm's. getStringRepresentation is not called from llvm itself, so far it is mostly a debugging aid, so the shorter strings are an independent improvement. llvm-svn: 197740
* Ensure deterministic when printing ARM assembler constant poolsDavid Peixotto2013-12-191-12/+24
| | | | | | | | | | | | | | | | We dump any non-empty assembler constant pools after a successful parse of an assembly file that uses the ldr pseudo opcode. These per-section constant pools should be output in a deterministic order to ensure that we always generate the same output when printing the output with an AsmStreamer. This patch changes the map data struture used to associate a section with its constant pool to a MapVector to ensure deterministic output. Because this map type does not support deletion, we now check that the constant pool is not empty before dumping its entries and clear the entries after emitting them with the streamer. llvm-svn: 197735
* Revert my change to the X86 assembler for intel syntax to work withKevin Enderby2013-12-192-50/+2
| | | | | | directional labels. Because it doesn't work for windows :) llvm-svn: 197731
* Changed the X86 assembler for intel syntax to work with directional labels.Kevin Enderby2013-12-192-2/+50
| | | | | | | | | | | | | | | | | | | | | | | The X86 assembler has a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following the Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197728
* Update the links to the SPARC information.Rafael Espindola2013-12-191-2/+3
| | | | llvm-svn: 197719
* Make sys::ThreadLocal<> zero-initialized on non-thread builds (PR18205)Hans Wennborg2013-12-194-2/+41
| | | | | | | | | | | | | According to the docs, ThreadLocal<>::get() should return NULL if no object has been set. This patch makes that the case also for non-thread builds and adds a very basic unit test to check it. (This was causing PR18205 because PrettyStackTraceHead didn't get zero- initialized and we'd crash trying to read past the end of that list. We didn't notice this so much on Linux since we'd crash after printing all the entries, but on Mac we print into a SmallString, and would crash before printing that.) llvm-svn: 197718
* Stay classy (and legal) LLVM. Remove links to 3rd party SMT solver whose ↵Kay Tiong Khoo2013-12-191-4/+2
| | | | | | links may not be permanent. llvm-svn: 197713
* [X86][fast-isel] Fix select lowering.Quentin Colombet2013-12-192-2/+23
| | | | | | | | | | The condition in selects is supposed to be i1. Make sure we are just reading the less significant bit of the 8 bits width value to match this constraint. <rdar://problem/15651765> llvm-svn: 197712
* Implement the .ltorg directive for ARM assemblyDavid Peixotto2013-12-193-0/+310
| | | | | | | | | | | | This directive will write out the assembler-maintained constant pool for the current section. These constant pools are created to support the ldr-pseudo instruction (e.g. ldr r0, =val). The directive can be used by the programmer to place the constant pool in a location that can be reached by a pc-relative offset in the ldr instruction. llvm-svn: 197711
* Unbreak ARM buildbots after r197653 by forcing the target triple on this test.Josh Magee2013-12-191-1/+1
| | | | llvm-svn: 197709
* Implement the ldr-pseudo opcode for ARM assemblyDavid Peixotto2013-12-195-1/+582
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ldr-pseudo opcode is a convenience for loading 32-bit constants. It is converted into a pc-relative load from a constant pool. For example, ldr r0, =0x10001 ldr r1, =bar will generate this output in the final assembly ldr r0, .Ltmp0 ldr r1, .Ltmp1 ... .Ltmp0: .long 0x10001 .Ltmp1: .long bar Sketch of the LDR pseudo implementation: Keep a map from Section => ConstantPool When parsing ldr r0, =val parse val as an MCExpr get ConstantPool for current Section Label = CreateTempSymbol() remember val in ConstantPool at next free slot add operand to ldr that is MCSymbolRef of Label On finishParse() callback Write out all non-empty constant pools for each Entry in ConstantPool Emit Entry.Label Emit Entry.Value Possible improvements to be added in a later patch: 1. Does not convert load of small constants to mov (e.g. ldr r0, =0x1 => mov r0, 0x1) 2. Does reuse constant pool entries for same constant The implementation was tested for ARM, Thumb1, and Thumb2 targets on linux and darwin. llvm-svn: 197708
* Add a finishParse() callback to the targer asm parserDavid Peixotto2013-12-192-0/+9
| | | | | | | | This callback is invoked when the parse has finished successfuly. It will be used to write out ARM constant pools to implement the ldr pseudo. llvm-svn: 197706
* Improved fix for PR17827 (instcombine of shift/and/compare).Kay Tiong Khoo2013-12-191-22/+32
| | | | | | | | | This change fixes the case of arithmetic shift right - do not attempt to fold that case. This change also relaxes the conditions when attempting to fold the logical shift right and shift left cases. No additional IR-level test cases included at this time. See http://llvm.org/bugs/show_bug.cgi?id=17827 for proofs that these are correct transformations. llvm-svn: 197705
* Revert r197682, "[CMake] Introduce LIT in add_lit_target."NAKAMURA Takumi2013-12-191-5/+2
| | | | llvm-svn: 197703
* Move testcase to the appropriate X86 subdirectory.Adrian Prantl2013-12-191-0/+0
| | | | llvm-svn: 197701
* Small simplification, p0 is the same as p.Rafael Espindola2013-12-191-1/+1
| | | | llvm-svn: 197699
* Support for microMIPS control instructions.Zoran Jovanovic2013-12-195-25/+158
| | | | llvm-svn: 197696
* Long doubles are required to be aligned to 128 bits and svr4 32 bits.Rafael Espindola2013-12-191-4/+0
| | | | | | Clang was already getting this right. llvm-svn: 197694
* Add a disassembler to the PowerPC backendHal Finkel2013-12-1919-3/+4352
| | | | | | | | | | | | | | | | | | | | | The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
* Support for microMIPS LL and SC instructions.Zoran Jovanovic2013-12-196-6/+51
| | | | llvm-svn: 197692
* Add support for positionally-encoded operands to FixedLenDecoderEmitterHal Finkel2013-12-192-4/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, the PowerPC instruction definitions make heavy use of the positional operand encoding heuristic to map operands onto bitfield variables in the instruction definitions. Changing this to use name-based mapping is not trivial, however, because additional infrastructure needs to be designed to handle mapping of complex operands (with multiple suboperands) onto multiple bitfield variables. In the mean time, this adds support for positionally encoded operands to FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC backend. To prevent an accidental reliance on this feature, and to prevent an undesirable interaction with existing disassemblers, a backend must opt-in to this support by setting the new decodePositionallyEncodedOperands instruction-set bit to true. When enabled, this iterates the variables that contribute to the instruction encoding, just as the encoder does, and emulates the procedure the encoder uses to map "numbered" operands to variables. The bit range for each variable is also determined as the encoder determines them. This map is then consulted during the decoder-generator's loop over operands to decode, allowing the decoder to understand both position-based and name-based operand-to-variable mappings. As noted in the comment on the decodePositionallyEncodedOperands definition, this support should be removed once it is no longer needed. There should be no change to existing disassemblers. llvm-svn: 197691
* Add a triple so that this passes on OS X.Rafael Espindola2013-12-191-1/+1
| | | | | | I am surprised I am the first one to notice this. llvm-svn: 197689
* Support for microMIPS TLS relocations.Zoran Jovanovic2013-12-197-2/+34
| | | | llvm-svn: 197685
* llvm-config: Don't show build tree with --obj-root for installed ↵NAKAMURA Takumi2013-12-191-1/+1
| | | | | | llvm-config. Show $(prefix) instead. llvm-svn: 197684
* llvm-config: Show build root instead of parent path in build tree with ↵NAKAMURA Takumi2013-12-191-0/+1
| | | | | | --obj-root for CMake multiconfig. llvm-svn: 197683
* [CMake] Introduce LIT in add_lit_target.NAKAMURA Takumi2013-12-191-2/+5
| | | | llvm-svn: 197682
* Add support for PointerLikeRegClass to FixedLenDecoderEmitterHal Finkel2013-12-191-0/+4
| | | | | | | | This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter should recognize PointerLikeRegClass operands as register types, and generate register-like decoding calls instead of treating them like immediates. llvm-svn: 197680
* [dfsan] Simplify code after r197677.Evgeniy Stepanov2013-12-191-19/+14
| | | | llvm-svn: 197679
* Add an explicit insert point argument to SplitBlockAndInsertIfThen.Evgeniy Stepanov2013-12-196-42/+62
| | | | | | | | Currently SplitBlockAndInsertIfThen requires that branch condition is an Instruction itself, which is very inconvenient, because it is sometimes an Operator, or even a Constant. llvm-svn: 197677
* Teach the llvm-readobj COFF dumper to dump debug line tables from object filesTimur Iskhodzhanov2013-12-199-0/+459
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D2425 llvm-svn: 197674
* Remove the COFF files with Z7 debug info from the repoTimur Iskhodzhanov2013-12-194-0/+0
| | | | | | | Rationale: going to land D2425 shortly. I'll re-land these COFF files along with D2425 to simplify the SVN history llvm-svn: 197673
* Add REQUIRES:asserts to 3 tests in llvm/test/CodeGen/R600 added in r192212.NAKAMURA Takumi2013-12-193-0/+3
| | | | | | They are failing in assertions. llvm-svn: 197669
* llvm-config: Introduce --system-libs to print SYSTEM_LIBS, and deprecate ↵NAKAMURA Takumi2013-12-191-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | SYSTEM_LIBS in --ldflags. Although --system-libs is expected to use after --libs, it can be used alone. $ bin/llvm-config --ldflags -L/path/to/llvm/objroot/lib $ bin/llvm-config --libs object -lLLVMObject -lLLVMSupport $ bin/llvm-config --system-libs (Blank line. "all" is assumed but nothing is printed.) -lrt -ldl -ltinfo -lpthread -lz $ bin/llvm-config --ldflags --libs --system-libs object -L/path/to/llvm/objroot/lib -lLLVMObject -lLLVMSupport -lrt -ldl -ltinfo -lpthread -lz It is reimplementation of r197380, and workaround for PR3347 and PR8449. FIXME: Each LLVM component may have its dependent system libs. llvm-svn: 197664
* GCOV.cpp: Fix format strings, %lf. Don't use %lf to double.NAKAMURA Takumi2013-12-191-3/+3
| | | | llvm-svn: 197663
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