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* [APFloat] Removed APFloat constructor which initialized to either zero/NaN ↵Michael Gottesman2013-06-273-20/+9
| | | | | | | | | | | | | | but allowed you to arbitrarily set the category of the float. The category which an APFloat belongs to should be dependent on the actual value that the APFloat has, not be arbitrarily passed in by the user. This will prevent inconsistency bugs where the category and the actual value in APFloat differ. I also fixed up all of the references to this constructor (which were only in LLVM). llvm-svn: 185095
* Improve the compression of the tablegen DiffLists by introducing a new sortChad Rosier2013-06-274-22/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 llvm-svn: 185094
* [Support/Registry.h] Include llvm/Support/Compiler.h.Argyrios Kyrtzidis2013-06-271-0/+2
| | | | | | Because Registry.h is using the LLVM_DELETED_FUNCTION macro. llvm-svn: 185087
* Get rid of the unused class member.Nadav Rotem2013-06-271-3/+2
| | | | llvm-svn: 185086
* CostModel: improve the cost model for load/store of non power-of-two types ↵Nadav Rotem2013-06-272-0/+62
| | | | | | such as <3 x float>, which are popular in graphics. llvm-svn: 185085
* R600: Remove alu-split.ll testTom Stellard2013-06-271-851/+0
| | | | | | | | | | | | | | | The purpose of this test was to check boundary conditions for the size of an ALU clause. This test is very sensitive to changes to the optimizer or scheduler, because it requires an exact number of ALU instructions in order to remain valid. It's not good to have a test this sensitive, because it is confusing to developers who implement optimizations and then 'break' the test. I'm not sure if there is a good way to test these limits using lit, but if I can come up with replacement test that isn't as sensitive I'll add it back to the tree. llvm-svn: 185084
* LoopVectorize: Use vectorized loop invariant gep index anchored in loopArnold Schwaighofer2013-06-272-8/+56
| | | | | | | | | Use vectorized instruction instead of original instruction anchored in the original loop. Fixes PR16452 and t2075.c of PR16455. llvm-svn: 185081
* Use MCFillFragment for zero-initialized data.Serge Pavlov2013-06-275-8/+21
| | | | | | | | It fixes PR16338 (ICE when compiling very large two-dimensional array). Differential Revision: http://llvm-reviews.chandlerc.com/D1043 llvm-svn: 185080
* Add a Subtarget feature 'v8fp' to the ARM backend.Joey Gouly2013-06-277-5/+36
| | | | llvm-svn: 185073
* Remove unused variable.Benjamin Kramer2013-06-271-2/+0
| | | | llvm-svn: 185072
* Don't cast away constness.Benjamin Kramer2013-06-271-1/+2
| | | | llvm-svn: 185071
* [SystemZ] Fix some embarrassing test typosRichard Sandiford2013-06-2714-30/+30
| | | | llvm-svn: 185070
* [SystemZ] Allow LA and LARL to be rematerializedRichard Sandiford2013-06-274-4/+36
| | | | llvm-svn: 185069
* [SystemZ] Allow immediate moves to be rematerializedRichard Sandiford2013-06-278-39/+94
| | | | llvm-svn: 185068
* [SystemZ] Add conditional store patternsRichard Sandiford2013-06-2713-9/+1910
| | | | | | | | | | | | | | | | | | | | | Add pseudo conditional store instructions, so that we use: branch foo: store foo: instead of: load branch foo: move foo: store z196 has real 32-bit and 64-bit conditional stores, but we don't use any z196 instructions yet. llvm-svn: 185065
* Add more owners to CODE_OWNERS.TXT (Kostya Serebryany: AddressSanitizer and ↵Kostya Serebryany2013-06-271-0/+8
| | | | | | ThreadSanitizer; Evgeniy Stepanov: MemorySanitizer) llvm-svn: 185064
* Update testing case to make DI nodes have the correct format.Manman Ren2013-06-271-3/+3
| | | | llvm-svn: 185061
* Add CXXFLAGS back to the Link command.Bob Wilson2013-06-271-1/+2
| | | | | | | | This is essentially reverting one piece of 184793 to try to fix one of Apple's buildbots. I will check with Eric to see if this is OK or if we need to find some other solution. llvm-svn: 185060
* Add a convenience createUniqueDirectory function.Rafael Espindola2013-06-274-12/+20
| | | | | | | | | | | There are a few valid situation where we care about the structure inside a directory, but not about the directory itself. A simple example is for unit testing directory traversal. PathV1 had a function like this, add one to V2 and port existing users of the created temp file and delete it hack to using it. llvm-svn: 185059
* Fix spelling.Arnold Schwaighofer2013-06-271-1/+1
| | | | llvm-svn: 185052
* LoopVectorize: Don't store a reversed value in the vectorized value mapArnold Schwaighofer2013-06-272-1/+59
| | | | | | | | | | When we store values for reversed induction stores we must not store the reversed value in the vectorized value map. Another instruction might use this value. This fixes 3 test cases of PR16455. llvm-svn: 185051
* [APFloat] Added unittest for APFloat.divide that checks special cases, ↵Michael Gottesman2013-06-271-0/+304
| | | | | | result categories, and result statuses. llvm-svn: 185050
* Added support for the Builtin attribute.Michael Gottesman2013-06-2715-23/+154
| | | | | | | | The Builtin attribute is an attribute that can be placed on function call site that signal that even though a function is declared as being a builtin, rdar://problem/13727199 llvm-svn: 185049
* No need to use a Set when a vector would do.Nadav Rotem2013-06-271-3/+3
| | | | llvm-svn: 185047
* Removed two logging printf statements from the APFloat tests... = /.Michael Gottesman2013-06-271-8/+0
| | | | llvm-svn: 185045
* [APFloat] Added unittest for APFloat.multiply that checks special cases, ↵Michael Gottesman2013-06-261-0/+307
| | | | | | result categories, and result status. llvm-svn: 185044
* [APFloat] Added unittest for APFloat.subtract that checks special cases, ↵Michael Gottesman2013-06-261-0/+303
| | | | | | result categories, and result status. llvm-svn: 185043
* SLP: When searching for vectorization opportunities scan the blocks in ↵Nadav Rotem2013-06-261-2/+4
| | | | | | post-order because we grow chains upwards. llvm-svn: 185041
* SLP: Dont erase instructions during vectorization because it prevents the ↵Nadav Rotem2013-06-261-2/+0
| | | | | | outerloops from iterating over the instructions. llvm-svn: 185040
* In InstCombine{AddSub,MulDivRem} convert APFloat.isFiniteNonZero() && ↵Michael Gottesman2013-06-262-5/+5
| | | | | | !APFloat.isDenormal => APFloat.isNormal. llvm-svn: 185037
* [APFloat] Convert all references to fcNormal to references to isFiniteNonZero().Michael Gottesman2013-06-261-30/+30
| | | | | | | | | | | | Currently inside APFloat fcNormal still implies the old definition of Normal (i.e. isFiniteNonZero) instead of the proper IEEE-754R definition that the external method isNormal() uses. This patch prepares for the internal switch inside APFloat by converting all references that check if a category is fcNormal directly with an indirect call via isFiniteNonZero(). llvm-svn: 185036
* Revert "Debug Info: clean up usage of Verify." as it's breaking bots.Eric Christopher2013-06-264-8/+8
| | | | | | This reverts commit r185020 llvm-svn: 185032
* Fix a crash bug in dumping options with groupsReid Kleckner2013-06-261-4/+6
| | | | | | | | Option groups don't have prefixes. Option dumping is basically dead code unless there is something wrong with the option table, so this isn't an important crasher. llvm-svn: 185031
* Clarify and doxygen-ify commentsStephen Lin2013-06-262-16/+20
| | | | llvm-svn: 185030
* [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-265-17/+20
| | | | | | | function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. llvm-svn: 185026
* ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is ↵Stephen Lin2013-06-263-4/+23
| | | | | | | | not used for incompatible calling conventions. (Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such) llvm-svn: 185024
* Debug Info: clean up usage of Verify.Manman Ren2013-06-264-8/+8
| | | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. llvm-svn: 185020
* Minor formatting fix to ARMBaseRegisterInfo::getCalleeSavedRegsStephen Lin2013-06-261-7/+5
| | | | llvm-svn: 185016
* Rename PathV2 to just Path now that it is the only one.Rafael Espindola2013-06-264-11/+11
| | | | llvm-svn: 185015
* [mips] Do not emit ".option pic0" if target is mips64.Akira Hatanaka2013-06-262-1/+3
| | | | llvm-svn: 185012
* [mips] Improve code generation for constant multiplication using shifts, ↵Akira Hatanaka2013-06-262-0/+103
| | | | | | | | adds and subs. llvm-svn: 185011
* [APFloat] Removed debugging cruft that snuck in.Michael Gottesman2013-06-261-4/+0
| | | | llvm-svn: 184974
* The SLP Vectorizer works across basic blocks. Update the docs.Nadav Rotem2013-06-261-9/+7
| | | | llvm-svn: 184973
* Use enums instead of raw octal values.Rafael Espindola2013-06-263-4/+8
| | | | | | Patch by 罗勇刚(Yonggang Luo). llvm-svn: 184971
* Erase all of the instructions that we RAUWedNadav Rotem2013-06-262-1/+10
| | | | llvm-svn: 184969
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-269-11/+41
| | | | | | This allows for targeting the ARMv8 AArch32 variant. llvm-svn: 184967
* Do not add cse-ed instructions into the visited map because we dont want to ↵Nadav Rotem2013-06-262-5/+93
| | | | | | consider them as a candidate for replacement of instructions to be visited. llvm-svn: 184966
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-268-36/+100
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-265-28/+61
| | | | | | | The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. llvm-svn: 184964
* Remove the 'generic' CPU from the ARM eabi attributes printer.Joey Gouly2013-06-262-13/+5
| | | | | | Make v4 the default ARM architecture attribute, to match CodeGen. llvm-svn: 184962
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