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* [SchedModel] Remove an unneeded temporary vector.Craig Topper2018-03-241-3/+2
| | | | llvm-svn: 328442
* [SchedModel] Use std::move in a couple places to reduce copyingCraig Topper2018-03-241-2/+3
| | | | llvm-svn: 328441
* [SchedModel] Use std::move to replace a vector instead of vector::swapCraig Topper2018-03-241-1/+1
| | | | | | We don't really care about the old vector value so we don't care to swap it. llvm-svn: 328440
* [SchedModel] Remove std::vectors that were created with 1 element and then ↵Craig Topper2018-03-241-8/+5
| | | | | | | | passed to an ArrayRef parameter. ArrayRef can capture a single element. We don't need a vector for that. llvm-svn: 328438
* [SchedModel] Record::getName() returns StringRef - avoid std::string ↵Simon Pilgrim2018-03-241-2/+2
| | | | | | creation. NFCI. llvm-svn: 328437
* [SchedModel] Avoid std::string creation for instregex patterns that don't ↵Simon Pilgrim2018-03-241-2/+3
| | | | | | contain regex metas. NFCI. llvm-svn: 328436
* [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an ↵Craig Topper2018-03-243-17/+13
| | | | | | | | attribute. This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables. llvm-svn: 328416
* [X86] Use unique_ptr to simplify memory management. NFCCraig Topper2018-03-244-20/+14
| | | | llvm-svn: 328413
* [X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF ↵Craig Topper2018-03-241-24/+5
| | | | | | format encodings. NFC llvm-svn: 328412
* [X86] Remove an unnecessary switch around two other switches. NFCCraig Topper2018-03-241-69/+54
| | | | | | The outer switch only had one valid block so didn't provide any value. llvm-svn: 328411
* [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFCCraig Topper2018-03-242-12/+11
| | | | | | The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map. llvm-svn: 328410
* Fix layering of CodeGen/TargetOpcodes.def by moving it to SupportDavid Blaikie2018-03-231-1/+1
| | | | | | | It's also used by utils/TableGen so needs to reside somewhere common to TableGen and CodeGen. llvm-svn: 328396
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-237-10/+10
| | | | | | | | | This is used by llvm tblgen as well as by LLVM Targets, so the only common place is Support for now. (maybe we need another target for these sorts of things - but for now I'm at least making them correct & we can make them better if/when people have strong feelings) llvm-svn: 328395
* Fix layering by moving X86DisassemblerDecoderCommon to SupportDavid Blaikie2018-03-232-3/+3
| | | | | | | | | This is used from llvm tblgen and the X86Disassembler - the only common library (apart from TableGen, which probably doesn't make sense to have as a dependency from a release tool (rather than a use-while-building-llvm tool) of LLVM) llvm-svn: 328393
* [TableGen] Don't capture returned std::vectors by const reference.Craig Topper2018-03-231-12/+8
| | | | | | The full vector is being returned not a reference. So the reference was just a to a temporary. llvm-svn: 328275
* [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and ↵Craig Topper2018-03-221-4/+4
| | | | | | | | | | VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD This makes the Y position consistent with other instructions. This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary. llvm-svn: 328254
* vim: rename `singlethread` to `syncscope`Saleem Abdulrasool2018-03-221-1/+1
| | | | | | | SVN r307722 renamed the keyword from `singlethread` to `syncscope`. Update the syntax file accordingly. llvm-svn: 328211
* [TableGen] Use empty emplace_back to add defaulted constructed objects to ↵Craig Topper2018-03-221-10/+8
| | | | | | vectors to avoid using resize(size()+1). NFC llvm-svn: 328184
* [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via ↵Craig Topper2018-03-222-17/+13
| | | | | | emplace_back to create new SchedClasses instead of using resize(size+1) llvm-svn: 328183
* vim: add `dso_local` and `dso_preemptable` keywordsSaleem Abdulrasool2018-03-211-0/+2
| | | | | | Support the new keywords introduced in SVN r316668. llvm-svn: 328170
* [TableGen] Hoist the code for copying InstRWs from an old scheduling class ↵Craig Topper2018-03-211-12/+12
| | | | | | | | | | to a new one out of the loop that assigns instructions to the new class. NFCI We already know all the of instructions we're processing in the instruction loop belong to no class or all to the same class. So we only have to worry about remapping one class. So hoist it all out and remove the SmallPtrSet that tracked which class we'd already remapped. I had to introduce new instruction loop inside this code to print an error message, but that only occurs on the error path. llvm-svn: 328142
* [TableGen] Remove unnecessary map lookup and shadowing of a variable. NFCICraig Topper2018-03-211-1/+0
| | | | | | We already have an OldSCIdx variable in the outer loop here. And we already did the map lookup in the loop that populated ClassInstrs. And the outer OldSCIdx got it from ClassInstrs. llvm-svn: 328139
* [TableGen] Use range-based for loops. NFCCraig Topper2018-03-211-12/+11
| | | | llvm-svn: 328138
* [TableGen] Use count_if instead of a manual loop. NFCCraig Topper2018-03-211-5/+4
| | | | llvm-svn: 328137
* [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper directly. NFCI.Simon Pilgrim2018-03-211-1/+1
| | | | llvm-svn: 328128
* [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. ↵Simon Pilgrim2018-03-212-6/+4
| | | | | | NFCI. llvm-svn: 328126
* [TableGen] Remove a defaulted function argument that is never called with ↵Craig Topper2018-03-212-5/+3
| | | | | | another value. NFC llvm-svn: 328075
* [TableGen] Move a function from llvm namespace and make it a static ↵Craig Topper2018-03-212-9/+2
| | | | | | | | function. NFC It's only called from one place and is defined just above that use. llvm-svn: 328074
* [TableGen] Use SmallMapVector to simplify some code that was trying to keep ↵Craig Topper2018-03-211-14/+6
| | | | | | | | | | | | | | | | | | | | | a vector unique Summary: This code previously had a SmallVector of std::pairs containing an unsigned and another SmallVector. The outer vector was using the unsigned effectively as a key to decide which SmallVector to add into. So each time something new needed to be added the out vector needed to be scanned. If it wasn't found a new entry needed to be added to be added. This sounds very much like a map, but the next loop iterates over the outer vector to get a deterministic order. We can simplify this code greatly if use SmallMapVector instead. This uses more stack space since we now have a vector and a map, but the searching and creating new entries all happens behind the scenes. It should also make the search more efficient though usually there are only a few entries so that doesn't matter much. We could probably get determinism by just using std::map which would iterate over the unsigned key, but that would generate different output from what we get with the current implementation. Reviewers: RKSimon, dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44711 llvm-svn: 328070
* [SchedModel] Simplify InstRegexOp::apply. NFCI.Simon Pilgrim2018-03-201-24/+27
| | | | | | As discussed on D44687, there was no need for 2 separate for loops for collecting the Regex and then matching against instructions. llvm-svn: 328052
* [TableGen] Use range based for loop. NFCCraig Topper2018-03-201-5/+2
| | | | llvm-svn: 328034
* [TableGen] Use vector::append instead of looping and calling push_back. NFCCraig Topper2018-03-201-4/+2
| | | | | | Both vectors contain unsigned so we can just use append to do the copying. Not only is this shorter, but it should be able to predict the final size and only grow the vector once if needed. llvm-svn: 328033
* [TableGen] Use llvm::transform to simplify some loops. NFCICraig Topper2018-03-201-18/+12
| | | | llvm-svn: 328032
* [TableGen] Pass result of std::unique to vector::erase instead of ↵Craig Topper2018-03-201-2/+1
| | | | | | calculating a size and calling resize. llvm-svn: 328031
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-03-203-28/+81
| | | | | | | | | | | | | | | | | Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters that cover the low halves of these registers. This change adds artificial subregisters for the high halves in order to differentiate (in terms of register units) between the 32- and the low 16-bit registers. This patch contains parts that aim to preserve the calculated register pressure. This is in order to preserve the current codegen (minimize the impact of this patch). The approach of having artificial subregisters could be used to fix PR23423, but the pressure calculation would need to be changed. Differential Revision: https://reviews.llvm.org/D43353 llvm-svn: 328016
* build_llvm_package.bat: Drop LLDB from the package.Hans Wennborg2018-03-191-15/+7
| | | | | | | | | I don't think anyone ever got this to work, what with getting exactly the right Python dependency and so on. Removing it simplifies the script, removes a number of hairy dependencies, and cuts ~30 MB off the installer size. llvm-svn: 327835
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-181-1/+14
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* [TableGen] Remove unnecessary uses of make_range.Craig Topper2018-03-181-2/+2
| | | | llvm-svn: 327785
* [TableGen] Move some variables into for loop declaration. NFCCraig Topper2018-03-181-2/+1
| | | | | | They aren't needed after the loop. llvm-svn: 327784
* Fix some user facing typosSylvestre Ledru2018-03-172-3/+3
| | | | llvm-svn: 327776
* [X86] Added support for nocf_check attribute for indirect Branch TrackingOren Ben Simhon2018-03-171-0/+2
| | | | | | | | | | | | | | | X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET). IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp. The `nocf_check` attribute has two roles in the context of X86 IBT technology: 1. Appertains to a function - do not add ENDBR instruction at the beginning of the function. 2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction. This patch implements `nocf_check` context for Indirect Branch Tracking. It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks. Differential Revision: https://reviews.llvm.org/D41879 llvm-svn: 327767
* [UpdateTestChecks] Handle IR variables with a '-' in the nameAlexander Richardson2018-03-141-1/+2
| | | | | | | | | | | | | | | | | Summary: I noticed that clang will emit variables such as %indirect-arg-temp when running update_cc1_test_checks.py and therefore update_cc1_test_checks.py wasn't adding FileCheck captures for those variables. Reviewers: MaskRay Reviewed By: MaskRay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44459 llvm-svn: 327564
* Fix LLVM IR check lines in utils/update_cc_test_checks.pyFangrui Song2018-03-143-9/+11
| | | | | | | | | | Reviewers: arichardson Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44400 llvm-svn: 327538
* [lit] - Allow 1 test to report multiple micro-test results to provide ↵Brian Homerding2018-03-137-0/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | support for microbenchmarks. Summary: These changes are to allow to a Result object to have nested Result objects in order to support microbenchmarks. Currently lit is restricted to reporting one result object for one test, this change provides support tests that want to report individual timings for individual kernels. This revision is the result of the discussions in https://reviews.llvm.org/D32272#794759, https://reviews.llvm.org/D37421#f8003b27 and https://reviews.llvm.org/D38496. It is a separation of the changes purposed in https://reviews.llvm.org/D40077. This change will enable adding LCALS (Livermore Compiler Analysis Loop Suite) collection of loop kernels to the llvm test suite using the google benchmark library (https://reviews.llvm.org/D43319) with tracking of individual kernel timings. Previously microbenchmarks had been handled by using macros to section groups of microbenchmarks together and build many executables while still getting a grouped timing (MultiSource/TSVC). Recently the google benchmark library was added to the test suite and utilized with a litsupport plugin. However the limitation of 1 test 1 result limited its use to passing a runtime option to run only 1 microbenchmark with several hand written tests (MicroBenchmarks/XRay). This runs the same executable many times with different hand-written tests. I will update the litsupport plugin to utilize the new functionality (https://reviews.llvm.org/D43316). These changes allow lit to report micro test results if desired in order to get many precise timing results from 1 run of 1 test executable. Reviewers: MatzeB, hfinkel, rengolin, delcypher Differential Revision: https://reviews.llvm.org/D43314 llvm-svn: 327422
* update_mir_test_checks: Fix handling of IR input after r326284Justin Bogner2018-03-121-2/+2
| | | | llvm-svn: 327305
* [X86] Add all of the MRM_C0-MRM_FF forms to the switch in ↵Craig Topper2018-03-121-27/+20
| | | | | | | | | | RecognizableInstr::emitInstructionSpecifier. NFC Remove the special casing for MRM_F8 by using HANDLE_OPTIONAL. This should be NFC as the forms that were missing aren't used by any instructions today. They exist in the enum so that we didn't have to put them in one at a time when instructions are added. But looks like we failed here. llvm-svn: 327298
* utils: add a helper class to lit for captured substitutionsSaleem Abdulrasool2018-03-091-0/+19
| | | | | | | | | On Windows, if the substitution contains a back reference, it would removed due to the replacement of the escape character in lit. Create a helper class to avoid this which will simply ignore the replacement and mark the substitution as having capture groups being referenced. llvm-svn: 327082
* merge-request.sh: Update 6.0 metabug for 6.0.1Tom Stellard2018-03-081-1/+1
| | | | llvm-svn: 327024
* [MCSchedule] Always generate processor resource names.Andrea Di Biagio2018-03-081-2/+2
| | | | | | | | | | | | With this patch, the tablegen 'SubtargetEmitter' always generates processor resource names. The impact of this patch on the code size of other llvm tools is small. I have observed an average increase of 0.03% in code size when doing a release build of LLVM (on windows, using MSVC) with all the default backends. This change is done in preparation for the upcoming llvm-mca patch. llvm-svn: 326993
* [WebAssembly] Add except_ref as a first-class typeHeejin Ahn2018-03-081-0/+1
| | | | | | | | | | | | Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]]. Reviewers: dschuff Subscribers: jfb, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D43706 llvm-svn: 326985
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