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* switch AttrListPtr::get to take an ArrayRef, simplifying a lot of clients.Chris Lattner2012-05-281-1/+2
| | | | llvm-svn: 157556
* rdar://11542750 - llvm.trap should be marked no return.Chris Lattner2012-05-273-5/+28
| | | | llvm-svn: 157551
* Reimplement the intrinsic verifier to use the same table as ↵Chris Lattner2012-05-271-137/+0
| | | | | | | | | | | | | Intrinsic::getDefinition, making it stronger and more sane. Delete the code from tblgen that produced the old code. Besides being a path forward in intrinsic sanity, this also eliminates a bunch of machine generated code that was compiled into Function.o llvm-svn: 157545
* move some code around so that Verifier.cpp can get access to the intrinsic ↵Chris Lattner2012-05-271-33/+4
| | | | | | info table. llvm-svn: 157540
* enhance the intrinsic info table to encode what *kind* of Any argumentChris Lattner2012-05-271-12/+20
| | | | | | | it is (at the cost of 45 bytes of extra table space) so that the verifier can start using it. llvm-svn: 157536
* rearrange some code, no functionality change.Chris Lattner2012-05-261-20/+24
| | | | llvm-svn: 157523
* Compress MCRegisterInfo register name tables.Jakob Stoklund Olesen2012-05-251-3/+16
| | | | | | | Store (debugging) register names as offsets into a string table instead of as char pointers. llvm-svn: 157449
* Teach tblgen's set theory "sequence" operator to support an optional stride ↵Owen Anderson2012-05-241-3/+17
| | | | | | operand. llvm-svn: 157416
* Fixed typo in r156905.Patrik Hägglund2012-05-231-2/+2
| | | | llvm-svn: 157320
* small refinement to r157218 to save a tiny amount of table size in the commonChris Lattner2012-05-231-4/+10
| | | | | | case. llvm-svn: 157312
* Also compute TopoSigs in synthetic register classes.Jakob Stoklund Olesen2012-05-222-3/+8
| | | | | | | CodeGenRegisterClass has two constructors. Both need to compute the TopoSigs BitVector. llvm-svn: 157271
* Added address space qualifier to intrinsic PointerType arguments.Pete Cooper2012-05-211-0/+6
| | | | llvm-svn: 157218
* enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits ↵Chris Lattner2012-05-172-164/+75
| | | | | | | | | into a separate side table, using the handy SequenceToOffsetTable class. This encodes all these weird things into another 256 bytes, allowing all intrinsics to be encoded this way. llvm-svn: 156995
* finish encoding all of the interesting details of intrinsics. Now intrinsicsChris Lattner2012-05-171-45/+45
| | | | | | | are only rejected because they can't be encoded into a 32-bit unit, not because they contain an unencodable feature. llvm-svn: 156978
* strengthen the intrinsic descriptor stuff to be able to handle sin, cos and ↵Chris Lattner2012-05-171-54/+63
| | | | | | | | other intrinsics that use passed-in arguments. llvm-svn: 156977
* simplify code generated by tblgen that is not necessary since we droppedChris Lattner2012-05-171-20/+4
| | | | | | compatibility with LLVM 2.x bitcode files. llvm-svn: 156976
* I forgot the #ifdef _MSC_VER guard in my last commit.Francois Pichet2012-05-171-0/+5
| | | | llvm-svn: 156975
* Fix the MSVC 2010 build: disable the optimizer for a problematic function.Francois Pichet2012-05-171-0/+2
| | | | llvm-svn: 156973
* Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen2012-05-163-83/+54
| | | | | | | | | | | TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. llvm-svn: 156960
* Significantly reduce the compiled size of Functions.cpp by turning a big ↵Chris Lattner2012-05-161-117/+307
| | | | | | | | | | blob of tblgen generated code (for Intrinsic::getType) into a table. This handles common cases right now, but I plan to extend it to handle all cases and merge in type verification logic as well in follow-on patches. llvm-svn: 156905
* have tblgen emit cast<> instead of dyn_cast<> when we know it must succeed.Chris Lattner2012-05-161-2/+2
| | | | llvm-svn: 156902
* llvm-build: Add support for non-installed libraries (e.g., gtest).Daniel Dunbar2012-05-153-10/+24
| | | | | | | - These libraries are only reported by llvm-config when run from a development tree. llvm-svn: 156838
* llvm-build: Don't emit library information for disabled targets.Daniel Dunbar2012-05-152-1/+21
| | | | llvm-svn: 156837
* [utils] Fix Get{RepositoryPath,SourceVersion} to have a more robust is-git-svnDaniel Dunbar2012-05-152-2/+2
| | | | | | check. llvm-svn: 156836
* TableGen'erate mapping physical registers to encoding values.Jim Grosbach2012-05-151-4/+26
| | | | | | | | | | | Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. llvm-svn: 156829
* Create a struct representing register units in TableGen.Jakob Stoklund Olesen2012-05-152-35/+50
| | | | | | | | | | | | Besides the weight, we also want to store up to two root registers per unit. Most units will have a single root, the leaf register they represent. Units created for ad hoc aliasing get two roots: The two aliasing registers. The root registers can be used to compute the set of overlapping registers. llvm-svn: 156792
* Consider ad hoc aliasing when building RegUnits.Jakob Stoklund Olesen2012-05-141-12/+41
| | | | | | | | | | | | | | | | | | | | | | | Register units can be used to compute if two registers overlap: A overlaps B iff units(A) intersects units(B). With this change, the above holds true even on targets that use ad hoc aliasing (currently only ARM). This means that register units can be used to implement regsOverlap() more efficiently, and the register allocator can use the concept to model interference. When there is no ad hoc aliasing, the register units correspond to the maximal cliques in the register overlap graph. This is optimal, no other register unit assignment can have fewer units. With ad hoc aliasing, weird things are possible, and we don't try too hard to compute the maximal cliques. The current approach is always correct, and it works very well (probably optimally) as long as the ad hoc aliasing doesn't have cliques larger than pairs. It seems unlikely that any target would need more. llvm-svn: 156763
* Record the ad hoc aliasing graph in CodeGenRegister.Jakob Stoklund Olesen2012-05-142-5/+21
| | | | | | | | | | | | | The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). llvm-svn: 156762
* Compute topological signatures of registers.Jakob Stoklund Olesen2012-05-142-8/+76
| | | | | | | | | | | | | | | TableGen creates new register classes and sub-register indices based on the sub-register structure present in the register bank. So far, it has been doing that on a per-register basis, but that is not very efficient. This patch teaches TableGen to compute topological signatures for registers, and use that to reduce the amount of redundant computation. Registers get the same TopoSig if they have identical sub-register structure. TopoSigs are not currently exposed outside TableGen. llvm-svn: 156761
* Speed up computeComposites() by using the new SubReg -> SubIdx map.Jakob Stoklund Olesen2012-05-121-12/+10
| | | | | | | TableGen doesn't need to search through the SubRegs map to find an inverse entry. llvm-svn: 156690
* Remove extraneous ; and the resulting warning.Bill Wendling2012-05-111-1/+1
| | | | llvm-svn: 156649
* Defer computation of SuperRegs.Jakob Stoklund Olesen2012-05-112-11/+36
| | | | | | | | Don't compute the SuperRegs list until the sub-register graph is completely finished. This guarantees that the list of super-registers is properly topologically ordered, and has no duplicates. llvm-svn: 156629
* Compute secondary sub-registers.Jakob Stoklund Olesen2012-05-102-3/+161
| | | | | | | | | | | | | | | | | | | | | | The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. llvm-svn: 156587
* Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen2012-05-102-19/+38
| | | | | | | | The .td files specify a tree of sub-registers. Store that tree as ExplicitSubRegs lists in CodeGenRegister instead of extracting it from the Record when needed. llvm-svn: 156555
* Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.Andrew Trick2012-05-101-4/+9
| | | | | | I initially assumed that the subreg graph was a tree. That may not be true. llvm-svn: 156524
* Fix warning text.Jakob Stoklund Olesen2012-05-091-1/+1
| | | | llvm-svn: 156521
* Compute a backwards SubReg -> SubRegIndex map for each register.Jakob Stoklund Olesen2012-05-092-0/+23
| | | | | | | | | | | | | | | | This mapping is for internal use by TableGen. It will not be exposed in the generated files. Unfortunately, the mapping is not completely well-defined. The X86 xmm registers appear with multiple sub-register indices in the ymm registers. This is because of the odd idempotent sub_sd and sub_ss sub-register indices. I hope to be able to eliminate them entirely, so we can require the sub-registers to form a tree. For now, just place the canonical sub_xmm index in the mapping, and ignore the idempotents. llvm-svn: 156519
* Rename getSubRegs() to computeSubRegs().Jakob Stoklund Olesen2012-05-092-10/+11
| | | | | | That's what it does. llvm-svn: 156518
* Lit: rewind WinWaitReleased() stuff in TestRunner.NAKAMURA Takumi2012-05-081-60/+6
| | | | | | | | | | r145222 "lit/TestRunner.py: [Win32] Introduce WinWaitReleased(f), to wait for file handles to be released by children." r145223 "lit/TestRunner.py: Use RemoveForce()." r145381 "lit/TestRunner.py: Try to catch ERROR_FILE_NOT_FOUND, too." r152916 "lit/TestRunner.py: [Win32] Check all opened_files[] released, rather than (obsoleted) written_files[]." r153172 "lit/TestRunner.py: [Win32] Rework WinWaitReleased() again! "win32file" from Python Win32 Extensions." llvm-svn: 156381
* Make IntelJITEvents and OProfileJIT as optional libraries and addPreston Gurd2012-05-072-6/+37
| | | | | | | | | | | | optional library support to the llvm-build tool: - Add new command line parameter to llvm-build: “--enable-optional-libraries” - Add handing of new llvm-build library type “OptionalLibrary” - Update Cmake and automake build systems to pass correct flags to llvm-build based on configuration Patch by Dan Malea! llvm-svn: 156319
* TableGen: AsmMatcher diagnostic when missing instruction mnemonic.Jim Grosbach2012-05-061-0/+3
| | | | | | | Previously, if an instruction definition was missing the mnemonic, the next line would just assert(). Issue a real diagnostic instead. llvm-svn: 156263
* Order register classes by spill size first, members last.Jakob Stoklund Olesen2012-05-041-7/+7
| | | | | | | | | | | | This is still a topological ordering such that every register class gets a smaller enum value than its sub-classes. Placing the smaller spill sizes first makes a difference for the super-register class bit masks. When looking for a super-register class, we usually want the smallest possible kind of super-register. That is now available as the first bit set in the bit mask. llvm-svn: 156222
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-043-76/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. llvm-svn: 156151
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-34/+1
| | | | | | TargetRegisterClass now gives access to the necessary tables. llvm-svn: 156122
* Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen2012-05-031-4/+4
| | | | | | | | This is a pointer into one of the tables used by getMatchingSuperRegClass(). It makes it possible to use a shared implementation of that function. llvm-svn: 156121
* Emit SuperRegMasks as part of the existing SubClassMask arrays.Jakob Stoklund Olesen2012-05-031-102/+83
| | | | | | | | | The RC->getSubClassMask() pointer now points to a sequence of register class bit masks. The first bit mask is the normal sub-class mask. The following masks are super-reg class masks used by getMatchingSuperRegClass(). llvm-svn: 156120
* Compress tables for getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-19/+67
| | | | | | | | Many register classes only have a few super-registers, so it is not necessary to keep individual bit masks for all possible sub-register indices. llvm-svn: 156083
* Add the half type to the LLVM IR vim syntax highlighting.Owen Anderson2012-05-031-1/+1
| | | | llvm-svn: 156080
* Don't override subreg functions in targets without subregisters.Jakob Stoklund Olesen2012-05-031-42/+39
| | | | | | | | Some targets have no sub-registers at all. Use the TargetRegisterInfo versions of composeSubRegIndices(), getSubClassWithSubReg(), and getMatchingSuperRegClass() for those targets. llvm-svn: 156075
* Move llvm-tblgen's StringMatcher into the TableGen library so it canDouglas Gregor2012-05-025-206/+2
| | | | | | be used by clang-tblgen. llvm-svn: 156000
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