summaryrefslogtreecommitdiffstats
path: root/llvm/utils
Commit message (Collapse)AuthorAgeFilesLines
* [TableGen] Don't capture returned std::vectors by const reference.Craig Topper2018-03-231-12/+8
| | | | | | The full vector is being returned not a reference. So the reference was just a to a temporary. llvm-svn: 328275
* [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and ↵Craig Topper2018-03-221-4/+4
| | | | | | | | | | VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD This makes the Y position consistent with other instructions. This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary. llvm-svn: 328254
* vim: rename `singlethread` to `syncscope`Saleem Abdulrasool2018-03-221-1/+1
| | | | | | | SVN r307722 renamed the keyword from `singlethread` to `syncscope`. Update the syntax file accordingly. llvm-svn: 328211
* [TableGen] Use empty emplace_back to add defaulted constructed objects to ↵Craig Topper2018-03-221-10/+8
| | | | | | vectors to avoid using resize(size()+1). NFC llvm-svn: 328184
* [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via ↵Craig Topper2018-03-222-17/+13
| | | | | | emplace_back to create new SchedClasses instead of using resize(size+1) llvm-svn: 328183
* vim: add `dso_local` and `dso_preemptable` keywordsSaleem Abdulrasool2018-03-211-0/+2
| | | | | | Support the new keywords introduced in SVN r316668. llvm-svn: 328170
* [TableGen] Hoist the code for copying InstRWs from an old scheduling class ↵Craig Topper2018-03-211-12/+12
| | | | | | | | | | to a new one out of the loop that assigns instructions to the new class. NFCI We already know all the of instructions we're processing in the instruction loop belong to no class or all to the same class. So we only have to worry about remapping one class. So hoist it all out and remove the SmallPtrSet that tracked which class we'd already remapped. I had to introduce new instruction loop inside this code to print an error message, but that only occurs on the error path. llvm-svn: 328142
* [TableGen] Remove unnecessary map lookup and shadowing of a variable. NFCICraig Topper2018-03-211-1/+0
| | | | | | We already have an OldSCIdx variable in the outer loop here. And we already did the map lookup in the loop that populated ClassInstrs. And the outer OldSCIdx got it from ClassInstrs. llvm-svn: 328139
* [TableGen] Use range-based for loops. NFCCraig Topper2018-03-211-12/+11
| | | | llvm-svn: 328138
* [TableGen] Use count_if instead of a manual loop. NFCCraig Topper2018-03-211-5/+4
| | | | llvm-svn: 328137
* [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper directly. NFCI.Simon Pilgrim2018-03-211-1/+1
| | | | llvm-svn: 328128
* [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. ↵Simon Pilgrim2018-03-212-6/+4
| | | | | | NFCI. llvm-svn: 328126
* [TableGen] Remove a defaulted function argument that is never called with ↵Craig Topper2018-03-212-5/+3
| | | | | | another value. NFC llvm-svn: 328075
* [TableGen] Move a function from llvm namespace and make it a static ↵Craig Topper2018-03-212-9/+2
| | | | | | | | function. NFC It's only called from one place and is defined just above that use. llvm-svn: 328074
* [TableGen] Use SmallMapVector to simplify some code that was trying to keep ↵Craig Topper2018-03-211-14/+6
| | | | | | | | | | | | | | | | | | | | | a vector unique Summary: This code previously had a SmallVector of std::pairs containing an unsigned and another SmallVector. The outer vector was using the unsigned effectively as a key to decide which SmallVector to add into. So each time something new needed to be added the out vector needed to be scanned. If it wasn't found a new entry needed to be added to be added. This sounds very much like a map, but the next loop iterates over the outer vector to get a deterministic order. We can simplify this code greatly if use SmallMapVector instead. This uses more stack space since we now have a vector and a map, but the searching and creating new entries all happens behind the scenes. It should also make the search more efficient though usually there are only a few entries so that doesn't matter much. We could probably get determinism by just using std::map which would iterate over the unsigned key, but that would generate different output from what we get with the current implementation. Reviewers: RKSimon, dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44711 llvm-svn: 328070
* [SchedModel] Simplify InstRegexOp::apply. NFCI.Simon Pilgrim2018-03-201-24/+27
| | | | | | As discussed on D44687, there was no need for 2 separate for loops for collecting the Regex and then matching against instructions. llvm-svn: 328052
* [TableGen] Use range based for loop. NFCCraig Topper2018-03-201-5/+2
| | | | llvm-svn: 328034
* [TableGen] Use vector::append instead of looping and calling push_back. NFCCraig Topper2018-03-201-4/+2
| | | | | | Both vectors contain unsigned so we can just use append to do the copying. Not only is this shorter, but it should be able to predict the final size and only grow the vector once if needed. llvm-svn: 328033
* [TableGen] Use llvm::transform to simplify some loops. NFCICraig Topper2018-03-201-18/+12
| | | | llvm-svn: 328032
* [TableGen] Pass result of std::unique to vector::erase instead of ↵Craig Topper2018-03-201-2/+1
| | | | | | calculating a size and calling resize. llvm-svn: 328031
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-03-203-28/+81
| | | | | | | | | | | | | | | | | Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters that cover the low halves of these registers. This change adds artificial subregisters for the high halves in order to differentiate (in terms of register units) between the 32- and the low 16-bit registers. This patch contains parts that aim to preserve the calculated register pressure. This is in order to preserve the current codegen (minimize the impact of this patch). The approach of having artificial subregisters could be used to fix PR23423, but the pressure calculation would need to be changed. Differential Revision: https://reviews.llvm.org/D43353 llvm-svn: 328016
* build_llvm_package.bat: Drop LLDB from the package.Hans Wennborg2018-03-191-15/+7
| | | | | | | | | I don't think anyone ever got this to work, what with getting exactly the right Python dependency and so on. Removing it simplifies the script, removes a number of hairy dependencies, and cuts ~30 MB off the installer size. llvm-svn: 327835
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-181-1/+14
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* [TableGen] Remove unnecessary uses of make_range.Craig Topper2018-03-181-2/+2
| | | | llvm-svn: 327785
* [TableGen] Move some variables into for loop declaration. NFCCraig Topper2018-03-181-2/+1
| | | | | | They aren't needed after the loop. llvm-svn: 327784
* Fix some user facing typosSylvestre Ledru2018-03-172-3/+3
| | | | llvm-svn: 327776
* [X86] Added support for nocf_check attribute for indirect Branch TrackingOren Ben Simhon2018-03-171-0/+2
| | | | | | | | | | | | | | | X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET). IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp. The `nocf_check` attribute has two roles in the context of X86 IBT technology: 1. Appertains to a function - do not add ENDBR instruction at the beginning of the function. 2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction. This patch implements `nocf_check` context for Indirect Branch Tracking. It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks. Differential Revision: https://reviews.llvm.org/D41879 llvm-svn: 327767
* [UpdateTestChecks] Handle IR variables with a '-' in the nameAlexander Richardson2018-03-141-1/+2
| | | | | | | | | | | | | | | | | Summary: I noticed that clang will emit variables such as %indirect-arg-temp when running update_cc1_test_checks.py and therefore update_cc1_test_checks.py wasn't adding FileCheck captures for those variables. Reviewers: MaskRay Reviewed By: MaskRay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44459 llvm-svn: 327564
* Fix LLVM IR check lines in utils/update_cc_test_checks.pyFangrui Song2018-03-143-9/+11
| | | | | | | | | | Reviewers: arichardson Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44400 llvm-svn: 327538
* [lit] - Allow 1 test to report multiple micro-test results to provide ↵Brian Homerding2018-03-137-0/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | support for microbenchmarks. Summary: These changes are to allow to a Result object to have nested Result objects in order to support microbenchmarks. Currently lit is restricted to reporting one result object for one test, this change provides support tests that want to report individual timings for individual kernels. This revision is the result of the discussions in https://reviews.llvm.org/D32272#794759, https://reviews.llvm.org/D37421#f8003b27 and https://reviews.llvm.org/D38496. It is a separation of the changes purposed in https://reviews.llvm.org/D40077. This change will enable adding LCALS (Livermore Compiler Analysis Loop Suite) collection of loop kernels to the llvm test suite using the google benchmark library (https://reviews.llvm.org/D43319) with tracking of individual kernel timings. Previously microbenchmarks had been handled by using macros to section groups of microbenchmarks together and build many executables while still getting a grouped timing (MultiSource/TSVC). Recently the google benchmark library was added to the test suite and utilized with a litsupport plugin. However the limitation of 1 test 1 result limited its use to passing a runtime option to run only 1 microbenchmark with several hand written tests (MicroBenchmarks/XRay). This runs the same executable many times with different hand-written tests. I will update the litsupport plugin to utilize the new functionality (https://reviews.llvm.org/D43316). These changes allow lit to report micro test results if desired in order to get many precise timing results from 1 run of 1 test executable. Reviewers: MatzeB, hfinkel, rengolin, delcypher Differential Revision: https://reviews.llvm.org/D43314 llvm-svn: 327422
* update_mir_test_checks: Fix handling of IR input after r326284Justin Bogner2018-03-121-2/+2
| | | | llvm-svn: 327305
* [X86] Add all of the MRM_C0-MRM_FF forms to the switch in ↵Craig Topper2018-03-121-27/+20
| | | | | | | | | | RecognizableInstr::emitInstructionSpecifier. NFC Remove the special casing for MRM_F8 by using HANDLE_OPTIONAL. This should be NFC as the forms that were missing aren't used by any instructions today. They exist in the enum so that we didn't have to put them in one at a time when instructions are added. But looks like we failed here. llvm-svn: 327298
* utils: add a helper class to lit for captured substitutionsSaleem Abdulrasool2018-03-091-0/+19
| | | | | | | | | On Windows, if the substitution contains a back reference, it would removed due to the replacement of the escape character in lit. Create a helper class to avoid this which will simply ignore the replacement and mark the substitution as having capture groups being referenced. llvm-svn: 327082
* merge-request.sh: Update 6.0 metabug for 6.0.1Tom Stellard2018-03-081-1/+1
| | | | llvm-svn: 327024
* [MCSchedule] Always generate processor resource names.Andrea Di Biagio2018-03-081-2/+2
| | | | | | | | | | | | With this patch, the tablegen 'SubtargetEmitter' always generates processor resource names. The impact of this patch on the code size of other llvm tools is small. I have observed an average increase of 0.03% in code size when doing a release build of LLVM (on windows, using MSVC) with all the default backends. This change is done in preparation for the upcoming llvm-mca patch. llvm-svn: 326993
* [WebAssembly] Add except_ref as a first-class typeHeejin Ahn2018-03-081-0/+1
| | | | | | | | | | | | Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]]. Reviewers: dschuff Subscribers: jfb, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D43706 llvm-svn: 326985
* Add attributes and fix some keywords in llvm-mode.elFangrui Song2018-03-081-5/+23
| | | | | | | | | | | | Reviewers: rafael, echristo Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44135 llvm-svn: 326978
* TableGen: Use DefInit::getDef() instead of the type's getRecord()Nicolai Haehnle2018-03-051-14/+11
| | | | | | | | | | | The former simply makes more sense: we want to access the data here in the backend, not information about the type. More importantly, removing users of RecordRecTy::getRecord() allows us more freedom to refactor the frontend. Change-Id: Iee8905fd22cdb9b11c42ca03246c03d8fe4dd77f llvm-svn: 326699
* [utils] Add utils/update_cc_test_checks.pyFangrui Song2018-03-023-3/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A utility to update LLVM IR in C/C++ FileCheck test files. Example RUN lines in .c/.cc test files: // RUN: %clang -S -Os -DXX %s -o - | FileCheck %s // RUN: %clangxx -S -Os %s -o - | FileCheck -check-prefix=IR %s Usage: % utils/update_cc_test_checks.py --llvm-bin=release/bin test/a.cc % utils/update_cc_test_checks.py --c-index-test=release/bin/c-index-test --clang=release/bin/clang /tmp/c/a.cc // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang -emit-llvm -S -Os -DXX %s -o - | FileCheck -check-prefix=AA %s // RUN: %clangxx -emit-llvm -S -Os %s -o - | FileCheck -check-prefix=BB %s using T = #ifdef XX int __attribute__((vector_size(16))) #else short __attribute__((vector_size(16))) #endif ; // AA-LABEL: _Z3fooDv4_i: // AA: entry: // AA-NEXT: %add = shl <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1> // AA-NEXT: ret <4 x i32> %add // // BB-LABEL: _Z3fooDv8_s: // BB: entry: // BB-NEXT: %add = shl <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> // BB-NEXT: ret <8 x i16> %add T foo(T a) { return a + a; } Differential Revision: https://reviews.llvm.org/D42712 llvm-svn: 326591
* Losen time contraint to accommodate system loadsLei Huang2018-02-281-1/+1
| | | | llvm-svn: 326359
* update_mir_test_checks: Use the regexes from UpdateTestChecks.commonJustin Bogner2018-02-282-18/+17
| | | | | | | | | Some of the update_*_test_checks regexes have been moved into a library, so we might as well use them in update_mir_test_checks. Also includes minor bugfixes to the regexes that are there so we don't regress update_mir_test_checks llvm-svn: 326288
* update_mir_test_checks: Drop support for vreg block checksJustin Bogner2018-02-281-24/+9
| | | | | | | | | | Since vregs are printed in the instruction stream now, checking the vreg block is always redundant. Remove the temporary feature that allowed us to do that. This reverts r316134 llvm-svn: 326284
* Revert r326092: [gtest] Add PrintTo overload for StringRef.Ilya Biryukov2018-02-261-13/+0
| | | | | | | | | It seems to break the following buildbot: http://lab.llvm.org:8011/builders/sanitizer-windows/builds/24729 Will resubmit after investigating and fixing it. llvm-svn: 326096
* [gtest] Add PrintTo overload for StringRef.Ilya Biryukov2018-02-261-0/+13
| | | | | | | | | | | | | | | | Summary: It was printed using code for generic containers before, resulting in unreadable output. Reviewers: sammccall, labath Reviewed By: sammccall, labath Subscribers: labath, zturner, llvm-commits Differential Revision: https://reviews.llvm.org/D43330 llvm-svn: 326092
* Shrink various scheduling tables by using narrower types.Benjamin Kramer2018-02-231-7/+12
| | | | | | 16 bits ought to be enough for everyone. This shrinks clang by ~1MB. llvm-svn: 325941
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-233-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* Resubmit r325107 (case folding DJB hash)Pavel Labath2018-02-211-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue was that the has function was generating different results depending on the signedness of char on the host platform. This commit fixes the issue by explicitly using an unsigned char type to prevent sign extension and adds some extra tests. The original commit message was: This patch implements a variant of the DJB hash function which folds the input according to the algorithm in the Dwarf 5 specification (Section 6.1.1.4.5), which in turn references the Unicode Standard (Section 5.18, "Case Mappings"). To achieve this, I have added a llvm::sys::unicode::foldCharSimple function, which performs this mapping. The implementation of this function was generated from the CaseMatching.txt file from the Unicode spec using a python script (which is also included in this patch). The script tries to optimize the function by coalescing adjecant mappings with the same shift and stride (terms I made up). Theoretically, it could be made a bit smarter and merge adjecant blocks that were interrupted by only one or two characters with exceptional mapping, but this would save only a couple of branches, while it would greatly complicate the implementation, so I deemed it was not worth it. Since we assume that the vast majority of the input characters will be US-ASCII, the folding hash function has a fast-path for handling these, and only whips out the full decode+fold+encode logic if we encounter a character outside of this range. It might be possible to implement the folding directly on utf8 sequences, but this would also bring a lot of complexity for the few cases where we will actually need to process non-ascii characters. Reviewers: JDevlieghere, aprantl, probinson, dblaikie Subscribers: mgorny, hintonda, echristo, clayborg, vleschuk, llvm-commits Differential Revision: https://reviews.llvm.org/D42740 llvm-svn: 325732
* [vim] Recognize more FileCheck commentsMikhail Maltsev2018-02-201-0/+1
| | | | | | | | | | | | | | | | | Summary: Currently vim syntax highlighting recognizes 'CHECK:' as a special comment, but not CHECK-DAG, CHECK-NOT and other CHECKs. This patch adds rules for these comments. Reviewers: chandlerc, compnerd, rogfer01 Reviewed By: rogfer01 Subscribers: rogfer01, llvm-commits Differential Revision: https://reviews.llvm.org/D43289 llvm-svn: 325599
* Fix signed/unsigned comparison warning in AsmGenMatcher generated code. NFCI.Simon Pilgrim2018-02-171-4/+4
| | | | llvm-svn: 325428
* Remove "--full-shutdown" and instead use an environment variable LLD_IN_TEST.Rui Ueyama2018-02-161-3/+0
| | | | | | | | | | | | | | | | | We are running lld tests with "--full-shutdown" option because we don't want to call _exit() in lld if it is running tests. Regular shutdown is needed for leak sanitizer. This patch changes the way how we tell lld that it is running tests. Now "--full-shutdown" is removed, and LLD_IN_TEST environment variable is used instead. This patch enables full shutdown on all ports, e.g. ELF, COFF and wasm. Previously, we enabled it only for ELF. Differential Revision: https://reviews.llvm.org/D43410 llvm-svn: 325413
OpenPOWER on IntegriCloud