summaryrefslogtreecommitdiffstats
path: root/llvm/utils
Commit message (Collapse)AuthorAgeFilesLines
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-163-6/+35
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). llvm-svn: 182034
* Use proper syntax.Bill Wendling2013-05-151-1/+1
| | | | llvm-svn: 181930
* Add lldb and polly to the projects to tag.Bill Wendling2013-05-151-2/+3
| | | | llvm-svn: 181925
* Add 'CHECK-DAG' supportMichael Liao2013-05-141-23/+147
| | | | | | Refer to 'FileCheck.rst'f for details of 'CHECK-DAG'. llvm-svn: 181827
* Refactor string checking. No functionality change.Michael Liao2013-05-141-62/+94
| | | | llvm-svn: 181824
* Get the unittests compiling when building with cmake and the settingDuncan Sands2013-05-141-0/+4
| | | | | | -DLLVM_ENABLE_THREADS=false. llvm-svn: 181788
* Add libcxx and clang-tools-extra to the testing thing.Bill Wendling2013-05-081-3/+10
| | | | llvm-svn: 181418
* Add clang-tools-extra to the list of things to tag for the release.Bill Wendling2013-05-081-2/+2
| | | | llvm-svn: 181402
* Add the libc++ project to those we tag.Bill Wendling2013-05-071-2/+2
| | | | llvm-svn: 181371
* Try to fix ProgramTest on FreeBSDReid Kleckner2013-04-301-0/+5
| | | | | | | This seemed like the cleanest way to find the test executable. Also fix the file mode. llvm-svn: 180770
* Handle tied sub-operands in AsmMatcherEmitterUlrich Weigand2013-04-271-30/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem this patch addresses is the handling of register tie constraints in AsmMatcherEmitter, where one operand is tied to a sub-operand of another operand. The typical scenario for this to happen is the tie between the "write-back" register of a pre-inc instruction, and the base register sub-operand of the memory address operand of that instruction. The current AsmMatcherEmitter code attempts to handle tied operands by emitting the operand as usual first, and emitting a CVT_Tied node when handling the second (tied) operand. However, this really only works correctly if the tied operand does not have sub-operands (and isn't a sub-operand itself). Under those circumstances, a wrong MC operand list is generated. In discussions with Jim Grosbach, it turned out that the MC operand list really ought not to contain tied operands in the first place; instead, it ought to consist of exactly those operands that are named in the AsmString. However, getting there requires significant rework of (some) targets. This patch fixes the immediate problem, and at the same time makes one (small) step in the direction of the long-term solution, by implementing two changes: 1. Restricts the AsmMatcherEmitter handling of tied operands to apply solely to simple operands (not complex operands or sub-operand of such). This means that at least we don't get silently corrupt MC operand lists as output. However, if we do have tied sub-operands, they would now no longer be handled at all, except for: 2. If we have an operand that does not occur in the AsmString, and also isn't handled as tied operand, simply emit a dummy MC operand (constant 0). This works as long as target code never attempts to access MC operands that do no not occur in the AsmString (and are not tied simple operands), which happens to be the case for all targets where this situation can occur (ARM and PowerPC). [ Note that this change means that many of the ARM custom converters are now superfluous, since the implement the same "hack" now performed already by common code. ] Longer term, we ought to fix targets to never access *any* MC operand that does not occur in the AsmString (including tied simple operands), and then finally completely remove all such operands from the MC operand list. Patch approved by Jim Grosbach. llvm-svn: 180677
* Use 'git svn find-rev' in git-svnrevert instead of shell script fu.Michael Gottesman2013-04-261-4/+3
| | | | | | Thanks Chandler! llvm-svn: 180592
* Added the scripts git-svnup/git-svnrevert to utils/git-svn.Michael Gottesman2013-04-262-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | It makes more sense to have git-svnup here than catting said file in the documentation (where we should rather point users to this directory). I included git-svnrevert as an additional gift to the community. I will update the documentation in a second commit later today. git-svnrevert takes in a git hash for a commit, looks up the svn revision for said commit and then creates the normal git revert commit message with the one liner message, except instead of saying Revert "<<<INSERT ONELINER HERE>>>" This reverts commit <<<INSERT GITHASH HERE>>> It says: Revert "<<<INSERT ONELINER HERE>>>" This reverts commit r<<<INSERT SVN REVISION HERE>>> so git hashes will not escape into our svn logs (which just look unseemly). llvm-svn: 180587
* Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.Michael Liao2013-04-251-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Pattern has source location by itself. After adding a trivial method to retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns. One thing revised after this is the diagnostic info is more accurate by pointing to the start of the CHECK-NOT pattern instead of the end of the CHECK-NOT pattern. E.g. diagnostic message previously looks like <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:16: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ is changed to <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:12: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ llvm-svn: 180578
* Remove tailing whitespacesMichael Liao2013-04-251-1/+1
| | | | llvm-svn: 180564
* Machine model: Generate table entries for super-resources.Andrew Trick2013-04-231-14/+23
| | | | | | | | | Super-resources and resource groups are two ways of expressing overlapping sets of processor resources. Now we generate table entries the same way for both so the scheduler never needs to explicitly check for super-resources. llvm-svn: 180162
* Machine model: verify well-formed processor resource groups.Andrew Trick2013-04-232-0/+54
| | | | llvm-svn: 180161
* Machine model: rewrite a tablegen loop to avoid comparing record pointers.Andrew Trick2013-04-231-8/+4
| | | | llvm-svn: 180160
* [asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier2013-04-181-20/+45
| | | | | | | | variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
* lit: Fix infinite recursion when an out-of-tree test root is located inside ↵Daniel Dunbar2013-04-125-9/+47
| | | | | | the source test root. llvm-svn: 179402
* lit: Add a test for discovery w/ test_exec_root (out-of-tree test root).Daniel Dunbar2013-04-123-9/+60
| | | | llvm-svn: 179401
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-17/+19
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* lit: Don't descend into .git directories during test discovery.Daniel Dunbar2013-04-111-1/+1
| | | | llvm-svn: 179249
* lit: Shorten a metavar to make --help look nicer.Daniel Dunbar2013-04-111-1/+1
| | | | llvm-svn: 179248
* lit: Add a test for discovery when exact test names are given.Daniel Dunbar2013-04-111-0/+15
| | | | llvm-svn: 179247
* lit: Add a trivial test of the basic progress bar.Daniel Dunbar2013-04-116-0/+22
| | | | llvm-svn: 179243
* Move yaml2obj to tools too.Rafael Espindola2013-04-054-733/+1
| | | | llvm-svn: 178904
* Use ScalarBitSetTraits.Rafael Espindola2013-04-051-83/+84
| | | | | | What was missing was were the type strong operator|. llvm-svn: 178879
* Move obj2yaml to tools to sort out make's dependencies.Rafael Espindola2013-04-056-509/+1
| | | | llvm-svn: 178835
* Build obj2yaml with configure+make.Rafael Espindola2013-04-051-1/+1
| | | | llvm-svn: 178833
* Add back parsing of header charactestics.Rafael Espindola2013-04-041-1/+37
| | | | | | | | It had been dropped during the switch to yaml::IO. Also add a test going from yaml2obj to llvm-readobj. It can be extended as we add more fields/formats to yaml2obj. llvm-svn: 178786
* Remove anonymous namespace.Rafael Espindola2013-04-031-4/+0
| | | | | | | | | | | Looks like the gcc in http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32/ doesn't like "not external linkage": /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h: In instantiation of 'const bool llvm::yaml::has_SequenceMethodTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::value': /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:281: instantiated from 'llvm::yaml::has_SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >' /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/utils/yaml2obj/yaml2obj.cpp:627: instantiated from here /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:243: error: 'llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size' is not a valid template argument for type 'size_t (*)(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' because function 'static size_t llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' has not external linkage llvm-svn: 178600
* Use yaml::IO in yaml2obj.cpp.Rafael Espindola2013-04-021-551/+346
| | | | | | | The generic structs and specializations will be refactored when obj2yaml is changed to use yaml::IO. llvm-svn: 178593
* Fix TableGen subtarget-emitter to handle A9/Swift.Andrew Trick2013-03-291-5/+11
| | | | | | | | A9 uses itinerary classes, Swift uses RW lists. This tripped some verification when we're expanding variants. I had to refine the verification a bit. llvm-svn: 178357
* Revert r178166. According to Howard, this code is actually ok.Dan Gohman2013-03-291-3/+1
| | | | llvm-svn: 178319
* Avoid undefined behavior from passing a std::vector's own contentsDan Gohman2013-03-271-1/+3
| | | | | | in as an argument to push_back. llvm-svn: 178166
* TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2013-03-262-2/+24
| | | | | | Allow variants to be defined only for some processors on a target. llvm-svn: 178074
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-8/+9
| | | | llvm-svn: 177888
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-242-0/+16
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. llvm-svn: 177844
* Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen2013-03-241-2/+24
| | | | | | | | | | | | This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ llvm-svn: 177834
* Allow direct value types in pattern definitions.Jakob Stoklund Olesen2013-03-232-5/+29
| | | | | | | | | | | | | | | | | Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. llvm-svn: 177828
* Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.Jakob Stoklund Olesen2013-03-232-21/+21
| | | | | | | | | | | | | | | | | | | | | A register class can appear as a leaf TreePatternNode with and without a name: (COPY_TO_REGCLASS GPR:$src, F8RC) In a named leaf node like GPR:$src, the register class provides type information for the named variable represented by the node. The TypeSet for such a node is the set of value types that the register class can represent. In an unnamed leaf node like F8RC above, the register class represents itself as a kind of immediate. Such a node has the type MVT::i32, we'll never create a virtual register representing it. This change makes it possible to remove the special handling of COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp. llvm-svn: 177825
* Plug a memory leak in FileCheck when the input file is empty.Benjamin Kramer2013-03-231-6/+6
| | | | llvm-svn: 177822
* Add TableGen ctags(1) emitter and helper script.Sean Silva2013-03-215-1/+561
| | | | | | | | | | | | | | | | | | | | | To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) llvm-svn: 177682
* [lit] Avoid CRLFs in bash scripts on WindowsReid Kleckner2013-03-201-1/+4
| | | | | | | | Native Windows Python will do line ending translation by default, which we don't want in bash scripts. If we're not native Windows Python, then 'b' is ignored. llvm-svn: 177602
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-192-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. llvm-svn: 177428
* TableGen fix for the new machine model.Andrew Trick2013-03-181-4/+6
| | | | | | | | Properly handle cases where a group of instructions have different SchedRW lists with the same itinerary class. This was supposed to work, but I left in an early break. llvm-svn: 177317
* Extract a method.Jakob Stoklund Olesen2013-03-182-41/+42
| | | | | | | This computes the type of an instruction operand or result based on the records in the instruction's ins and outs lists. llvm-svn: 177244
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-176-10/+10
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-163-205/+174
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
OpenPOWER on IntegriCloud