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* [globalisel][tablegen] Add support for C++ predicates on PatFrags and use it ↵Daniel Sanders2018-06-153-20/+115
| | | | | | | | | | | | | | | | | | | | | to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
* [NFC] chmod +x utils/update_analyze_test_checks.pyRoman Lebedev2018-06-151-0/+0
| | | | | | Looks like a simple oversight. llvm-svn: 334825
* [X86] Add 'Z' to the internal names of various EVEX instructions for overall ↵Craig Topper2018-06-151-8/+8
| | | | | | consistency. llvm-svn: 334785
* Revert r334764, as it breaks some botsFlorian Hahn2018-06-146-502/+503
| | | | llvm-svn: 334767
* [TableGen] Make TreePatternNode::getChild return a reference (NFC)Florian Hahn2018-06-146-503/+502
| | | | | | | | The return value of TreePatternNode::getChild is never null. This patch also updates various places that use return values of getChild to also use references. Those changes were suggested post-commit for D47463. llvm-svn: 334764
* [TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).Florian Hahn2018-06-141-21/+21
| | | | | | Those changes were suggested post-commit for D47463. llvm-svn: 334706
* [TableGen] Make getOnlyTree return a const ref (NFC)Florian Hahn2018-06-132-9/+11
| | | | | | | This avoids some unnecessary copies of shared_ptrs. Those changes were suggested post-commit for D47463. llvm-svn: 334656
* [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.Clement Courbet2018-06-131-2/+16
| | | | | | | | | | | | | | | | | | | | | Summary: For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files. For more obvious cases, I've ventured a fix. Some notes: - Exynos is especially fishy. - AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice. - The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit. Also see PR37310. Reviewers: RKSimon, craig.topper, javed.absar Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46356 llvm-svn: 334586
* utils/release: Add merge-git.shTom Stellard2018-06-131-0/+92
| | | | | | | | | | | | | | | Summary: This script allows you to use git to backport a commit to a stable branch while generating the exact same commit message (ignoring whitespace) that you would get from using the merge.sh script with svn. Reviewers: hansw Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47760 llvm-svn: 334568
* [X86] Mark all instructions that have masked store semantics with ↵Craig Topper2018-06-131-16/+2
| | | | | | | | NotMemoryFoldable. Remove dependency on SchedRW from memory table autogenerator. Previously we were whitelisting in instructions based on their SchedRW value. With the masked store instructions explicitly removed via NotMemoryFoldable, we don't seem to need this check anymore. llvm-svn: 334563
* [X86] Remove unnecessary include from one of the tblgen emitters.Craig Topper2018-06-121-1/+0
| | | | llvm-svn: 334530
* Refactor ExecuteAndWait to take StringRefs.Zachary Turner2018-06-121-1/+5
| | | | | | | | | | | | | | | | | | | This simplifies some code which had StringRefs to begin with, and makes other code more complicated which had const char* to begin with. In the end, I think this makes for a more idiomatic and platform agnostic API. Not all platforms launch process with null terminated c-string arrays for the environment pointer and argv, but the api was designed that way because it allowed easy pass-through for posix-based platforms. There's a little additional overhead now since on posix based platforms we'll be takign StringRefs which were constructed from null terminated strings and then copying them to null terminate them again, but from a readability and usability standpoint of the API user, I think this API signature is strictly better. llvm-svn: 334518
* [X86] Don't add stores to the autogenerated load folding tables if the ↵Craig Topper2018-06-121-1/+2
| | | | | | | | register and memory operands have different widths. This can cause the amount of the memory written to be changed which would be bad. llvm-svn: 334480
* [X86] Update folding table generator to properly detect RMW arithmetic ↵Craig Topper2018-06-121-2/+4
| | | | | | | | | | instructions. The RMW instructions are detected by reading the SchedRW data, but the RMW instructions have had their SchedRW changed in recent months. This broke the expectation. We probably should fix this to use the mayLoad/mayStore flags if possible. llvm-svn: 334478
* [X86] Enforce agreement of AdSize field when autogenerating load folding ↵Craig Topper2018-06-121-0/+1
| | | | | | table entries. llvm-svn: 334473
* TableGen: Change some pointer parameters to references since they're never ↵David Blaikie2018-06-112-21/+22
| | | | | | null anyway llvm-svn: 334446
* [Utils] update_llc_test_checks.py: support AMDGPU backend: AMDGCN, r600 triplesRoman Lebedev2018-06-111-0/+19
| | | | | | | | | | | | | | | | | | | | | | | Summary: Lack of that support has taken me by surprise. I need to add (or at least look at) some tests for https://reviews.llvm.org/D47980#1127615, and i don't really fancy doing that by hand. The asm pattern is quite similar to that of x86: https://godbolt.org/g/hfgeds just with `#` replaced with `;` Reviewers: spatel, RKSimon, MaskRay, tstellar, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, rampitec, bogner, mareko, llvm-commits Tags: #amdgpu Differential Revision: https://reviews.llvm.org/D48001 llvm-svn: 334396
* [TableGen] Make better use of std::map::emplace and emplace construct the ↵Craig Topper2018-06-101-9/+10
| | | | | | object in the map rather than moving it into it. Remove a use std::map::find by remembering the return from emplace. llvm-svn: 334380
* [TableGen] Combine two constructors by taking vectors by value instead of ↵Craig Topper2018-06-101-11/+3
| | | | | | trying to support combininations for rvalue and lvalue references. llvm-svn: 334379
* Revert r334374 [TableGen] Move some shared_ptrs to avoid unnecessary copies ↵Florian Hahn2018-06-102-26/+21
| | | | | | | | (NFC). This breaks some builders. llvm-svn: 334376
* [TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).Florian Hahn2018-06-102-21/+26
| | | | | | Those changes were suggested post-commit for D47463. llvm-svn: 334374
* [tablegen] Improve performance on *GenRegisterInfo.inc by replacing ↵Daniel Sanders2018-06-081-3/+3
| | | | | | | | | | | | | | | | SparseVector with BitVector. NFC Summary: Generating X86GenRegisterInfo.inc and AArch64GenRegisterInfo.inc is 8-9% faster on my build. Reviewers: bogner, javed.absar Reviewed By: bogner Subscribers: llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D47907 llvm-svn: 334337
* [TableGen] Make DAGInstruction own Pattern to avoid leaking it.Florian Hahn2018-06-082-11/+13
| | | | | | | | | | Reviewers: dsanders, craig.topper, stoklund, nhaehnle Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47525 llvm-svn: 334275
* [X86] Rename vy512mem->vy512xmem and vz256xmem->vz256mem.Craig Topper2018-06-061-4/+4
| | | | | | | | | | | The index size is represented by the letter after the 'v'. The number represents the memory size. If an 'x' appears after the number its means the index register can be from VR128X/VR256X instead of VR128/VR256. As vy512mem uses a VR256X index it should have an x. And vz256mem uses a VR512 index so it shouldn't have an x. I admit these names kind of suck and are confusing. llvm-svn: 334120
* Relax shtest-run-at-line.pyHans Wennborg2018-06-062-18/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test was failing on Windows machines which had bash.exe on PATH (but not in the so called lit tools dir, containing cmp.exe, grep.exe etc.). The problem was that the outer lit invocation would load LLVMConfig from utils/lit/lit/llvm/config.py, which looks up the tools path with getToolsPath(). That has a surprising side effect of also setting bashPath, in our case setting it to empty. The outer lit invocation would thus configure the pdbg0 and pdbg1 substitutions based on not running with bash. But the inner lit invocation would not load LLVMConfig, so bash would be found on PATH, that would be used as external shell, and so the output wouldn't match pdbg0 and pdbg1. It seems weird to me that getBashPath() will return different results depending on whether getToolsPath() has been called before, but I also don't know how to fix it properly. This commit just relaxes the test case, because there doesn't seem to be much point in testing for the exact syntax of the run file as long as it works. (See https://crbug.com/850023) llvm-svn: 334100
* Avoid UnicodeEncodeError on non-ascii reviewer namesKristof Beyls2018-06-061-13/+13
| | | | | | | ... by using unicode instead of byte strings where non-ascii strings can be formatted in. llvm-svn: 334098
* [Analyzer] Fix the Z3 lit test configVlad Tsyrklevich2018-06-061-1/+1
| | | | | | | | | | | | | | | | | Summary: The '%analyze' extra_args config argument seems to have been erroneously deleted in r315627 disabling Z3 tests for the clang analyzer. Add the flag back. Reviewers: george.karpenkov, NoQ, ddcc Reviewed By: george.karpenkov Subscribers: xazax.hun, szepet, delcypher, a.sidorin, llvm-commits Differential Revision: https://reviews.llvm.org/D47722 llvm-svn: 334066
* [UpdateTestChecks] Error if --llvm-mca-binary gets an empty stringGreg Bedwell2018-06-051-0/+3
| | | | | | | | | | | If the command line was mistyped like: ./update_mca_test_checks.py --llvm-mca-binary= /path/to/llvm-mca *.s ^-- extra whitespace then /path/to/llvm-mca would get treated by argparse as a test-path pattern and could actually be opened in write mode and overwritten. llvm-svn: 334029
* TableGen/DAGPatterns: Allow bit constants in addition to int constantsNicolai Haehnle2018-06-041-3/+5
| | | | | | | | | | | | | | | Summary: Implicit casting is a simple quality of life improvement. Change-Id: I3d2b31b8b8f12cbb1e84f691e359fa713a9c4b42 Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D47432 llvm-svn: 333904
* [llvm-mca][UpdateTestChecks] Prevent an IndexError being raised when given ↵Greg Bedwell2018-06-041-1/+1
| | | | | | empty input llvm-svn: 333894
* [llvm-mca] Make sure not to end the test files with an empty line.Roman Lebedev2018-06-041-3/+5
| | | | | | | | | | | | | | | | | | | Summary: It's super irritating. [properly configured] git client then complains about that double-newline, and you have to use `--force` to ignore the warning, since even if you fix it manually, it will be reintroduced the very next runtime :/ Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell Reviewed By: gbedwell Subscribers: javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47697 llvm-svn: 333887
* [Utils][X86] Help update_llc_test_checks.py to recognise retl/retq to reduce ↵Simon Pilgrim2018-06-013-12/+33
| | | | | | | | | | | | | | | | CHECK duplication (PR35003) This patch replaces the --x86_extra_scrub command line argument to automatically support a second level of regex-scrubbing if it improves the matching of nearly-identical code patterns. The argument '--extra_scrub' is there now to force extra matching if required. This is mostly useful to help us share 32-bit/64-bit x86 vector tests which only differs by retl/retq instructions, but any scrubber can now technically support this, meaning test checks don't have to be needlessly obfuscated. I've updated some of the existing checks that had been manually run with --x86_extra_scrub, to demonstrate the extra "ret{{[l|q]}}" scrub now only happens when useful, and re-run the sse42-intrinsics file to show extra matches - most sse/avx intrinsics files should be able to now share 32/64 checks. Tested with the opt/analysis scripts as well which share common code - AFAICT the other update scripts use their own versions. Differential Revision: https://reviews.llvm.org/D47485 llvm-svn: 333749
* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-311-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* [lit] Fix windows cmd.exe test config for r333620Joel E. Denny2018-05-312-8/+8
| | | | llvm-svn: 333630
* [lit] Terminate ": RUN at line N" with ";" not "&&"Joel E. Denny2018-05-314-20/+20
| | | | | | | | This fixes projects/compiler-rt/test/fuzzer/sigusr.test, which was broken by r333614. The trouble was that "&&" changes the command for which "$!" gives the pid. llvm-svn: 333620
* [lit] Report line number for failed RUN commandJoel E. Denny2018-05-3116-11/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Relands r333584, reverted in 333592.) When debugging test failures with -vv (or -v in the case of the internal shell), this makes it easier to locate the RUN line that failed. For example, clang's test/Driver/linux-ld.c has 892 total RUN lines, and clang's test/Driver/arm-cortex-cpus.c has 424 RUN lines after concatenation for line continuations. When reading the generated shell script, this also makes it easier to locate the RUN line that produced each command. To support reporting RUN line numbers in the case of the internal shell, this patch extends the internal shell to support the null command, ":", except pipelines are not supported. To support reporting RUN line numbers in the case of windows cmd.exe as the external shell, this patch extends -vv to set "echo on" instead of "echo off" in bat files. (Support for windows cmd.exe as a lit external shell will likely be dropped later, but I found out too late.) Reviewed By: delcypher, asmith, stella.stamenova, jmorse, lebedev.ri, rnk Differential Revision: https://reviews.llvm.org/D44598 llvm-svn: 333614
* Revert r333584: [lit] Report line number for failed RUN commandJoel E. Denny2018-05-3016-186/+17
| | | | | | It breaks test-suite. llvm-svn: 333592
* [TableGen] Avoid leaking TreePatternNodes by using shared_ptr.Florian Hahn2018-05-303-234/+229
| | | | | | | | | | | | By using std::shared_ptr for TreePatternNode, we can avoid leaking them. Reviewers: craig.topper, dsanders, stoklund, tstellar, zturner Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47463 llvm-svn: 333591
* [lit] Report line number for failed RUN commandJoel E. Denny2018-05-3016-17/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Relands r330755 (reverted in r330848) with fix for PR37239.) When debugging test failures with -vv (or -v in the case of the internal shell), this makes it easier to locate the RUN line that failed. For example, clang's test/Driver/linux-ld.c has 892 total RUN lines, and clang's test/Driver/arm-cortex-cpus.c has 424 RUN lines after concatenation for line continuations. When reading the generated shell script, this also makes it easier to locate the RUN line that produced each command. To support reporting RUN line numbers in the case of the internal shell, this patch extends the internal shell to support the null command, ":", except pipelines are not supported. To support reporting RUN line numbers in the case of windows cmd.exe as the external shell, this patch extends -vv to set "echo on" instead of "echo off" in bat files. (Support for windows cmd.exe as a lit external shell will likely be dropped later, but I found out too late.) Reviewed By: delcypher, asmith, stella.stamenova, jmorse, lebedev.ri, rnk Differential Revision: https://reviews.llvm.org/D44598 llvm-svn: 333584
* [TableGen] Use explicit constructor for InstMemoFlorian Hahn2018-05-291-2/+8
| | | | | | | This should fix a few buildbot failures with old GCC versions. llvm-svn: 333448
* [TableGen] Fix leaking of PhysRegInputs.Florian Hahn2018-05-291-13/+17
| | | | | | | | | | | | | Instead of dynamically allocating the vector for PhysRegs, we can allocate it on the stack and move it into InstructionMemo. Reviewers: mcrosier, craig.topper, RKSimon, dsanders Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47461 llvm-svn: 333438
* [TableGen] Fix leaking synthesized registers.Florian Hahn2018-05-292-2/+15
| | | | | | | | | | | | | By keeping track of unique_ptrs to the synthesized definitions in CodeGenRegBank we avoid leaking them. Reviewers: dsanders, kparzysz, stoklund Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47462 llvm-svn: 333434
* [Tablegen] Avoid generating empty switch statements. NFCAndrea Di Biagio2018-05-271-4/+10
| | | | | | | This fixes an MSVC warning (warning C4065: switch statement contains 'default' but no 'case' labels) introduced with revision 333293. llvm-svn: 333363
* [Tablegen][SubtargetEmitter] Add a default case to the auto-generated switch ↵Andrea Di Biagio2018-05-251-1/+3
| | | | | | in MCSubtargetInfo::resolveVariantSchedClass(). NFC llvm-svn: 333293
* [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling ↵Andrea Di Biagio2018-05-252-1/+79
| | | | | | | | | | | | | | | | | | | | classes. This patch is the second of a sequence of three patches related to LLVM-dev RFC "MC support for varinat scheduling classes". https://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to enable the resolution of variant classes in MC with the help of a new method named `MCSubtargetInfo::resolveVariantSchedClass()`. This patch also teaches the SubtargetEmitter how to automatically generate the definition of method resolveVariantSchedClass(). That definition is emitted within a sub-class of MCSubtargetInfo named XXXGenMCSubtargetInfo (where XXX is the name of the Target). Differential Revision: https://reviews.llvm.org/D47077 llvm-svn: 333286
* [RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.Andrea Di Biagio2018-05-255-33/+447
| | | | | | | | | | | | | | | | | | | | | | This patch is the first of a sequence of three patches described by the LLVM-dev RFC "MC support for variant scheduling classes". http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to introduce a new class of scheduling predicates for SchedReadVariant and SchedWriteVariant. An MCSchedPredicate can be used instead of a normal SchedPredicate to model checks on the instruction (either a MachineInstr or a MCInst). Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition. MCInstPredicate allows the definition of expressions with a well-known semantic, that can be used to generate code for both MachineInstr and MCInst. This is the first step toward teaching to tools like lllvm-mca how to resolve variant scheduling classes. Differential Revision: https://reviews.llvm.org/D46695 llvm-svn: 333282
* Use quoteattr to ensure we make well formed attributesChris Matthews2018-05-254-38/+40
| | | | | | | | We were making malformed XML on tests with ' in the name. Switch to using saxutils to set all of our attributes, so it can handle quotes etc correctly. llvm-svn: 333249
* [UpdateTestChecks] Improved update_mca_test_checks block analysisGreg Bedwell2018-05-241-22/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously update_mca_test_checks worked entirely at "block" level where a block is some sequence of lines delimited by at least one empty line. This generally worked well, but could sometimes lead to excessive repetition of check lines for various prefixes if some block was almost identical between prefixes, but not quite (for example, due to a different dispatch width in the otherwise identical summary views). This new analyis attempts to split blocks further in the case where the following conditions are met: a) There is some prefix common to every RUN line (typically 'ALL'). b) The first line of the block is common to the output with every prefix. c) The block has the same number of lines for the output with every prefix. Also, regenerated all llvm-mca test files with the following command: update_mca_test_checks.py "../test/tools/llvm-mca/*/*.s" "../test/tools/llvm-mca/*/*/*.s" The new analysis showed a "multiple lines not disambiguated by prefixes" warning for test "AArch64/Exynos/scheduler-queue-usage.s" so I've also added some explicit prefixes to each of the RUN lines in that test. Differential Revision: https://reviews.llvm.org/D47321 llvm-svn: 333204
* [GlobalISel][InstructionSelect] Switching over root LLTs, perf patch 10Roman Tereshin2018-05-241-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | This patch continues a series of patches started by r332907 (reapplied as r332917). In this commit we introduce new matching opcode for the MatchTable: GIM_SwitchType, similar to GIM_SwitchOpcode, and use it to switch over LLTs of def operands of root instructions on the 2nd level of the MatchTable within GIM_SwitchOpcode's cases. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by about 6.5% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64 (cross-compile on x86). Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333146
* [GlobalISel][InstructionSelect] Moving Reg Bank Checks forward, perf patch 9Roman Tereshin2018-05-231-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch continues a series of patches started by r332907 (reapplied as r332917). In this commit we move register bank checks back from epilogue of every rule matcher to a position locally close to the rest of the checks for a particular (nested) instruction. This increases the number of common conditions within 2nd level groups. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by about 2% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64 (cross-compile on x86). Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333144
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