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* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-064-52/+41
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. llvm-svn: 163315
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-0/+2
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Constify subtarget info properly so that we dont cast away the const inRoman Divacky2012-09-051-1/+1
| | | | | | the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. llvm-svn: 163251
* Fix function name per coding standard.Chad Rosier2012-09-051-3/+3
| | | | llvm-svn: 163187
* Fix function name per coding standard.Chad Rosier2012-09-051-4/+4
| | | | llvm-svn: 163186
* [ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. ThisChad Rosier2012-09-041-1/+0
| | | | | | | implementation does not co-exist well with how the sideeffect and alignstack attributes are handled. The reverts r161641. llvm-svn: 163174
* [LIT] Add a clang_tools_extra_site_cfg to match the various other site_cfg.David Blaikie2012-09-041-4/+9
| | | | | | | | | This doesn't seem ideal, perhaps we could just keep the llvm_site_cfg and have other config (clang and clang-tools-extra) derive their site_cfg from that. Suggestions/complaints/ideas welcome. llvm-svn: 163171
* Fix Android build of gtest and lib/Support.Evgeniy Stepanov2012-09-041-1/+1
| | | | llvm-svn: 163131
* [ms-inline asm] Make comment more verbose and add an assert.Chad Rosier2012-09-031-1/+2
| | | | llvm-svn: 163125
* [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, addChad Rosier2012-09-031-2/+20
| | | | | | | the NumMCOperands argument to the GetMCInstOperandNum() function that is set to the number of MCOperands this asm operand mapped to. llvm-svn: 163124
* [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in theChad Rosier2012-09-031-6/+7
| | | | | | MCTargetAsmParser class. llvm-svn: 163122
* Remove extraneous return.Chad Rosier2012-09-031-1/+1
| | | | llvm-svn: 163119
* [ms-inline asm] Return the MCOperandNum instead of passing a reference.Chad Rosier2012-09-031-10/+9
| | | | llvm-svn: 163118
* Removed unused argument.Chad Rosier2012-09-031-5/+4
| | | | llvm-svn: 163104
* [ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier2012-09-031-5/+8
| | | | | | | | | | MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. llvm-svn: 163101
* Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()Chad Rosier2012-08-311-1/+1
| | | | | | function nowadays. llvm-svn: 163030
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-311-0/+2
| | | | llvm-svn: 162999
* With the fix in r162954/162955 every cvt function returns true. Thus, haveChad Rosier2012-08-311-13/+11
| | | | | | | the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. llvm-svn: 162961
* Whitespace.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162946
* Whitespace.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162945
* Hoist a check to eliminate obvious mismatches as early as possible. Also, fixChad Rosier2012-08-301-8/+8
| | | | | | an 80-column violation in the generated code. No functional change intended. llvm-svn: 162944
* [ms-inline asm] Add a new function, GetMCInstOperandNum, to theChad Rosier2012-08-301-1/+43
| | | | | | | | | | | | | | | | | | | | | | | AsmMatcherEmitter. This function maps inline assembly operands to MCInst operands. For example, '__asm mov j, eax' is represented by the follow MCInst: <MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>> The first 5 MCInst operands are a result of j matching as a memory operand consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0), Expr (Expr:(j), and a MemSegReg (Reg:0). The 6th MCInst operand represents the eax register (Reg:43). This translation is necessary to determine the Input and Output Exprs. If a single asm operand maps to multiple MCInst operands, the index of the first MCInst operand is returned. Ideally, it would return the operand we really care out (i.e., the Expr:(j) in this case), but I haven't found an easy way of doing this yet. llvm-svn: 162920
* Fix a nondeterminism in the ARM assembler.Andrew Trick2012-08-291-0/+9
| | | | | | | | | | Adding arbitrary records to ARM.td would break basic-arm-instructions.s because selection of nop vs mov r0,r0 was ambiguous (this will be tested by a subsequent addition to ARM.td). An imperfect but sensible fix is to give precedence to match rules that have more constraints. llvm-svn: 162824
* Check all patterns for missing instruction flags.Jakob Stoklund Olesen2012-08-282-0/+72
| | | | | | | Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. llvm-svn: 162734
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-12/+5
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Infer instruction properties from single-instruction patterns.Jakob Stoklund Olesen2012-08-241-0/+39
| | | | | | | | | | | | | | | | | | | | | Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. llvm-svn: 162614
* Stop inferring isVariadic from instruction patterns.Jakob Stoklund Olesen2012-08-241-1/+5
| | | | | | | | | | | | | | | | | | Instructions are now only marked as variadic if they use variable_ops in their ins list. A variadic SDNode is typically used for call nodes that have the call arguments as operands. A variadic MachineInstr can actually encode a variable number of operands, for example ARM's stm/ldm instructions. A call instruction does not have to be variadic. The call argument registers are added as implicit operands. This change remove the MCID::Variadic flags from most call and return instructions, allowing us to better verify their operands. llvm-svn: 162599
* Verify explicit instruction properties when they can be inferred.Jakob Stoklund Olesen2012-08-241-2/+39
| | | | | | | | | It is now allowed to explicitly set hasSideEffects, mayStore, and mayLoad on instructions with patterns. Verify that the patterns are consistent with the explicit flags. llvm-svn: 162569
* Heed guessInstructionProperties, and stop warning on redundant flags.Jakob Stoklund Olesen2012-08-243-93/+92
| | | | | | | | | | | | Emit TableGen errors if guessInstructionProperties is 0 and instruction properties can't be inferred from patterns. Allow explicit instruction properties even when they can be inferred. This patch doesn't change the TableGen output. Redundant properties are not yet verified because the tree has errors. llvm-svn: 162516
* Tristate mayLoad, mayStore, and hasSideEffects.Jakob Stoklund Olesen2012-08-232-4/+11
| | | | | | | Keep track of the set/unset state of these bits along with their true/false values, but treat '?' as '0' for now. llvm-svn: 162461
* Add CodeGenTarget::guessInstructionProperties.Jakob Stoklund Olesen2012-08-232-0/+13
| | | | | | | | | | | | Currently, TableGen just guesses instruction properties when it can't infer them form patterns. This adds a guessInstructionProperties flag to the instruction set definition that will be used to disable guessing. The flag is intended as a migration aid. It will be removed again when no more targets need their properties guessed. llvm-svn: 162460
* Fix a bunch of -Wdocumentation warnings.Dmitri Gribenko2012-08-232-3/+3
| | | | llvm-svn: 162446
* Print out the location of expanded multiclass defs in TableGen errors.Jakob Stoklund Olesen2012-08-224-5/+5
| | | | | | | | | | | | | | | | | | | When reporting an error for a defm, we would previously only report the location of the outer defm, which is not always where the error is. Now we also print the location of the expanded multiclass defs: lib/Target/X86/X86InstrSSE.td:2902:12: error: foo defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>, ^ lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128, ^ lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), ^ llvm-svn: 162409
* TblGen: Make asm-matcher ConvertToMCInst() table driven.Jim Grosbach2012-08-221-55/+177
| | | | | | | | | | | | No change in interface or functionality. Purely under-the-hood details of the generated function that change. The X86 assembly parser is reduced in size by over 15% and ARM by over 10%. No performance change by my measurements. llvm-svn: 162337
* Formatting. No functional change.Chad Rosier2012-08-211-2/+2
| | | | llvm-svn: 162292
* Add stub methods for mips assembly matcher. Akira Hatanaka2012-08-171-1/+3
| | | | | | Patch by Vladimir Medic. llvm-svn: 162124
* Declare some for loop indices inside the for loop statement.Craig Topper2012-08-171-20/+13
| | | | llvm-svn: 162085
* Fix up indentation of outputted decode function for readability.Craig Topper2012-08-171-8/+8
| | | | llvm-svn: 162082
* lit: Show actually created count of threads. The incorrect threads count is ↵NAKAMURA Takumi2012-08-171-3/+3
| | | | | | | | printed if the number of tests are less than the number of default threads. Thanks to Vinson Lee, reported in PR13620. llvm-svn: 162078
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-163-0/+3
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
* Add a CoveringSubRegIndices field to SubRegIndex records.Jakob Stoklund Olesen2012-08-151-9/+22
| | | | | | | This can be used to tell TableGen to use a specific SubRegIndex instead of synthesizing one when discovering all sub-registers. llvm-svn: 161982
* Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen2012-08-153-33/+30
| | | | | | | | | | | TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. llvm-svn: 161964
* Fix a const violation in the generated disassembler.Benjamin Kramer2012-08-151-2/+2
| | | | llvm-svn: 161940
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-281/+722
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Add some missing includes for the build against stdcxx.Joerg Sonnenberger2012-08-101-0/+1
| | | | llvm-svn: 161657
* Use the final .version number for LLVM_MINOR_VERSION in Apple llvmCore builds.Bob Wilson2012-08-101-1/+1
| | | | | | | | We've switched to a 3-component version numbering scheme for Apple releases, and with this scheme, the final number is the one most relevant for setting LLVM_MINOR_VERSION. <rdar://problem/12071459> llvm-svn: 161645
* [ms-inline asm] Add a new Inline Asm Non-Standard Dialect attribute.Chad Rosier2012-08-101-0/+1
| | | | | | | | | | | | | | This new attribute is intended to be used by the backend to determine how the inline asm string should be parsed/printed. This patch adds the ia_nsdialect attribute and also adds a test case to ensure the IR is correctly parsed, but there is no functional change at this time. The standard dialect is assumed to be AT&T. Therefore, this attribute should only be added to MS-style inline assembly statements, which use the Intel dialect. If we ever support more dialects we'll need to add additional state to the attribute. llvm-svn: 161641
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-081-0/+1
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. llvm-svn: 161471
* Remove extraneous ';'.Bill Wendling2012-08-041-1/+1
| | | | llvm-svn: 161298
* Remove redundant '== true' after a comparison.Richard Trieu2012-08-021-1/+1
| | | | llvm-svn: 161223
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