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* Add missing dependency (headers are included from MC, so a link dependency ↵David Blaikie2018-03-291-1/+1
| | | | | | could exist easily enough) llvm-svn: 328743
* Revert "[lit] Temporarily disable shtest-timeout.py on darwin"Dan Liew2018-03-281-4/+1
| | | | | | | | | | This reverts commit 771829b640a5494ab65c810dd6b4330522bf3a33 (rr328598) Hopefully the test will now pass on the bots. rdar://problem/38774530 llvm-svn: 328703
* [lit] Remove a timing senstive part of `shtest-timeout.py`Dan Liew2018-03-282-52/+2
| | | | | | | | | | | | | | | | | | | | | | | The `shtest-timeout.py` test was failing intermittently. It looks like the issue is that on a resource constrained system lit is unable to run `quick_then_slow.py` twice and print out the messages the tests expects within the one second timeout. The underlying issue is that the test is dependent on the performance of the host machine is a rather fragile way. This is due to hardcoding timeout values and having assumptions that the host machine is able to perform a certain amount of work within the hardcoded timeout values. We could increase the timeout values but that doesn't really fix the underlying issue. Instead this patch removes one of fragile assumptions in the hope that this will be enough to fix the bots. There are other fragile assumptions in this test (e.g. `quick.py` can be executed in less than 1 second). If the bots continue to fail we'll have to revisit this. rdar://problem/38774530 llvm-svn: 328702
* [MachineScheduler] Add itinerary to schedcover.py. Make default work in the ↵Craig Topper2018-03-271-7/+16
| | | | | | | | | | | | | | | | | | | | | command line filter Summary: This patch adds itinerary support to the schedcover.py script. I've been trying to use this script to figure out why SSE and AVX instructions are ending up in separate tablegen scheduler classes and sometimes its because we are using different itineraries. Rather than using None to indicate the default scheduler model, I now use the string "default". I had to hack around the sorting a little to keep "default" at the beginning. But this also makes it so you can specify "default" on the command line to just get the defaults I also fixed the regular expression code so that the no_default wasn't evaluated twice. Reviewers: RKSimon, atrick, jmolloy, javed.absar Reviewed By: javed.absar Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44834 llvm-svn: 328608
* Revert "Revert "[lit] Generalized /dev/null support on Windows.""Mircea Trofin2018-03-273-3/+32
| | | | | | | | | | | | | | | | | Summary: This reverts commit r328596. Checking if the arguments are strings before testing if they contain "/dev/null". Reviewers: rnk Reviewed By: rnk Subscribers: delcypher, llvm-commits Differential Revision: https://reviews.llvm.org/D44914 llvm-svn: 328603
* [lit] Temporarily disable shtest-timeout.py on darwinJan Korous2018-03-271-1/+4
| | | | | | | | Disabled until fixed in order to avoid random failures on green dragon. rdar://problem/38774530 llvm-svn: 328598
* Revert "[lit] Generalized /dev/null support on Windows."Mircea Trofin2018-03-263-32/+3
| | | | | | This reverts commit ca7fdbb974384ce5a05528b22a41d46b1cc13e92. llvm-svn: 328596
* [lit] Generalized /dev/null support on Windows.Mircea Trofin2018-03-263-3/+32
| | | | | | | | | | | | | | Generalized /dev/null remapping on Windows, and added test. Reviewers: rnk Reviewed By: rnk Subscribers: amccarth, zturner, delcypher, llvm-commits Differential Revision: https://reviews.llvm.org/D44771 llvm-svn: 328589
* [lit] Implement 'cat' command for internal shellReid Kleckner2018-03-268-12/+183
| | | | | | | | | | Fixes PR36449 Patch by Chamal de Silva Differential Revision: https://reviews.llvm.org/D43501 llvm-svn: 328563
* Migrate dockerfiles to use multi-stage builds.Ilya Biryukov2018-03-268-119/+48
| | | | | | | | | | | | | | | | | | | | Summary: We previously emulated multi-staged builds using two dockerfiles, native support from Docker allows us to merge them into one, simplifying our scripts. For more details about multi-stage builds, see: https://docs.docker.com/develop/develop-images/multistage-build/ Reviewers: mehdi_amini, klimek, sammccall Reviewed By: sammccall Subscribers: llvm-commits, ioeric, cfe-commits Differential Revision: https://reviews.llvm.org/D44787 llvm-svn: 328503
* [SchedModel] Remove instregex entries that don't match any instructionsSimon Pilgrim2018-03-251-2/+11
| | | | | | | | | | This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean. All the cases I encountered have now been fixed in trunk and this will ensure they don't get reintroduced. Differential Revision: https://reviews.llvm.org/D44687 llvm-svn: 328459
* [SchedModel] Remove an unneeded temporary vector.Craig Topper2018-03-241-3/+2
| | | | llvm-svn: 328442
* [SchedModel] Use std::move in a couple places to reduce copyingCraig Topper2018-03-241-2/+3
| | | | llvm-svn: 328441
* [SchedModel] Use std::move to replace a vector instead of vector::swapCraig Topper2018-03-241-1/+1
| | | | | | We don't really care about the old vector value so we don't care to swap it. llvm-svn: 328440
* [SchedModel] Remove std::vectors that were created with 1 element and then ↵Craig Topper2018-03-241-8/+5
| | | | | | | | passed to an ArrayRef parameter. ArrayRef can capture a single element. We don't need a vector for that. llvm-svn: 328438
* [SchedModel] Record::getName() returns StringRef - avoid std::string ↵Simon Pilgrim2018-03-241-2/+2
| | | | | | creation. NFCI. llvm-svn: 328437
* [SchedModel] Avoid std::string creation for instregex patterns that don't ↵Simon Pilgrim2018-03-241-2/+3
| | | | | | contain regex metas. NFCI. llvm-svn: 328436
* [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an ↵Craig Topper2018-03-243-17/+13
| | | | | | | | attribute. This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables. llvm-svn: 328416
* [X86] Use unique_ptr to simplify memory management. NFCCraig Topper2018-03-244-20/+14
| | | | llvm-svn: 328413
* [X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF ↵Craig Topper2018-03-241-24/+5
| | | | | | format encodings. NFC llvm-svn: 328412
* [X86] Remove an unnecessary switch around two other switches. NFCCraig Topper2018-03-241-69/+54
| | | | | | The outer switch only had one valid block so didn't provide any value. llvm-svn: 328411
* [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFCCraig Topper2018-03-242-12/+11
| | | | | | The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map. llvm-svn: 328410
* Fix layering of CodeGen/TargetOpcodes.def by moving it to SupportDavid Blaikie2018-03-231-1/+1
| | | | | | | It's also used by utils/TableGen so needs to reside somewhere common to TableGen and CodeGen. llvm-svn: 328396
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-237-10/+10
| | | | | | | | | This is used by llvm tblgen as well as by LLVM Targets, so the only common place is Support for now. (maybe we need another target for these sorts of things - but for now I'm at least making them correct & we can make them better if/when people have strong feelings) llvm-svn: 328395
* Fix layering by moving X86DisassemblerDecoderCommon to SupportDavid Blaikie2018-03-232-3/+3
| | | | | | | | | This is used from llvm tblgen and the X86Disassembler - the only common library (apart from TableGen, which probably doesn't make sense to have as a dependency from a release tool (rather than a use-while-building-llvm tool) of LLVM) llvm-svn: 328393
* [TableGen] Don't capture returned std::vectors by const reference.Craig Topper2018-03-231-12/+8
| | | | | | The full vector is being returned not a reference. So the reference was just a to a temporary. llvm-svn: 328275
* [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and ↵Craig Topper2018-03-221-4/+4
| | | | | | | | | | VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD This makes the Y position consistent with other instructions. This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary. llvm-svn: 328254
* vim: rename `singlethread` to `syncscope`Saleem Abdulrasool2018-03-221-1/+1
| | | | | | | SVN r307722 renamed the keyword from `singlethread` to `syncscope`. Update the syntax file accordingly. llvm-svn: 328211
* [TableGen] Use empty emplace_back to add defaulted constructed objects to ↵Craig Topper2018-03-221-10/+8
| | | | | | vectors to avoid using resize(size()+1). NFC llvm-svn: 328184
* [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via ↵Craig Topper2018-03-222-17/+13
| | | | | | emplace_back to create new SchedClasses instead of using resize(size+1) llvm-svn: 328183
* vim: add `dso_local` and `dso_preemptable` keywordsSaleem Abdulrasool2018-03-211-0/+2
| | | | | | Support the new keywords introduced in SVN r316668. llvm-svn: 328170
* [TableGen] Hoist the code for copying InstRWs from an old scheduling class ↵Craig Topper2018-03-211-12/+12
| | | | | | | | | | to a new one out of the loop that assigns instructions to the new class. NFCI We already know all the of instructions we're processing in the instruction loop belong to no class or all to the same class. So we only have to worry about remapping one class. So hoist it all out and remove the SmallPtrSet that tracked which class we'd already remapped. I had to introduce new instruction loop inside this code to print an error message, but that only occurs on the error path. llvm-svn: 328142
* [TableGen] Remove unnecessary map lookup and shadowing of a variable. NFCICraig Topper2018-03-211-1/+0
| | | | | | We already have an OldSCIdx variable in the outer loop here. And we already did the map lookup in the loop that populated ClassInstrs. And the outer OldSCIdx got it from ClassInstrs. llvm-svn: 328139
* [TableGen] Use range-based for loops. NFCCraig Topper2018-03-211-12/+11
| | | | llvm-svn: 328138
* [TableGen] Use count_if instead of a manual loop. NFCCraig Topper2018-03-211-5/+4
| | | | llvm-svn: 328137
* [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper directly. NFCI.Simon Pilgrim2018-03-211-1/+1
| | | | llvm-svn: 328128
* [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. ↵Simon Pilgrim2018-03-212-6/+4
| | | | | | NFCI. llvm-svn: 328126
* [TableGen] Remove a defaulted function argument that is never called with ↵Craig Topper2018-03-212-5/+3
| | | | | | another value. NFC llvm-svn: 328075
* [TableGen] Move a function from llvm namespace and make it a static ↵Craig Topper2018-03-212-9/+2
| | | | | | | | function. NFC It's only called from one place and is defined just above that use. llvm-svn: 328074
* [TableGen] Use SmallMapVector to simplify some code that was trying to keep ↵Craig Topper2018-03-211-14/+6
| | | | | | | | | | | | | | | | | | | | | a vector unique Summary: This code previously had a SmallVector of std::pairs containing an unsigned and another SmallVector. The outer vector was using the unsigned effectively as a key to decide which SmallVector to add into. So each time something new needed to be added the out vector needed to be scanned. If it wasn't found a new entry needed to be added to be added. This sounds very much like a map, but the next loop iterates over the outer vector to get a deterministic order. We can simplify this code greatly if use SmallMapVector instead. This uses more stack space since we now have a vector and a map, but the searching and creating new entries all happens behind the scenes. It should also make the search more efficient though usually there are only a few entries so that doesn't matter much. We could probably get determinism by just using std::map which would iterate over the unsigned key, but that would generate different output from what we get with the current implementation. Reviewers: RKSimon, dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44711 llvm-svn: 328070
* [SchedModel] Simplify InstRegexOp::apply. NFCI.Simon Pilgrim2018-03-201-24/+27
| | | | | | As discussed on D44687, there was no need for 2 separate for loops for collecting the Regex and then matching against instructions. llvm-svn: 328052
* [TableGen] Use range based for loop. NFCCraig Topper2018-03-201-5/+2
| | | | llvm-svn: 328034
* [TableGen] Use vector::append instead of looping and calling push_back. NFCCraig Topper2018-03-201-4/+2
| | | | | | Both vectors contain unsigned so we can just use append to do the copying. Not only is this shorter, but it should be able to predict the final size and only grow the vector once if needed. llvm-svn: 328033
* [TableGen] Use llvm::transform to simplify some loops. NFCICraig Topper2018-03-201-18/+12
| | | | llvm-svn: 328032
* [TableGen] Pass result of std::unique to vector::erase instead of ↵Craig Topper2018-03-201-2/+1
| | | | | | calculating a size and calling resize. llvm-svn: 328031
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-03-203-28/+81
| | | | | | | | | | | | | | | | | Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters that cover the low halves of these registers. This change adds artificial subregisters for the high halves in order to differentiate (in terms of register units) between the 32- and the low 16-bit registers. This patch contains parts that aim to preserve the calculated register pressure. This is in order to preserve the current codegen (minimize the impact of this patch). The approach of having artificial subregisters could be used to fix PR23423, but the pressure calculation would need to be changed. Differential Revision: https://reviews.llvm.org/D43353 llvm-svn: 328016
* build_llvm_package.bat: Drop LLDB from the package.Hans Wennborg2018-03-191-15/+7
| | | | | | | | | I don't think anyone ever got this to work, what with getting exactly the right Python dependency and so on. Removing it simplifies the script, removes a number of hairy dependencies, and cuts ~30 MB off the installer size. llvm-svn: 327835
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-181-1/+14
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* [TableGen] Remove unnecessary uses of make_range.Craig Topper2018-03-181-2/+2
| | | | llvm-svn: 327785
* [TableGen] Move some variables into for loop declaration. NFCCraig Topper2018-03-181-2/+1
| | | | | | They aren't needed after the loop. llvm-svn: 327784
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