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* Add libstd++-4.8 exceptions to ubsan_blacklist.txtSam Clegg2017-11-291-0/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D40589 llvm-svn: 319353
* Make check-lit tests respect LLVM_LIT_TOOLS_DIRGreg Bedwell2017-11-293-5/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D40520 llvm-svn: 319329
* [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, ↵Daniel Sanders2017-11-281-38/+82
| | | | | | | | | | G_ATOMICRMW_* rules from SelectionDAG. GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider range of orderings. This has then been used to import patterns using nodes such as atomic_cmp_swap, atomic_swap, and atomic_load_*. llvm-svn: 319232
* lit: Bring back -Dtool=xxx feature lost in r313928Matthias Braun2017-11-281-3/+8
| | | | llvm-svn: 319139
* [utils][mips] Add support for mips for update_llc_checks.pySimon Dardis2017-11-261-0/+20
| | | | | | | | | | | Add support for mips, particularly skipping the matching of .frame, .(f)mask and LLVM's usage of the .set no(reorder|at|macro) directives. Reviewers: spatel Differential Revision: https://reviews.llvm.org/D40268 llvm-svn: 319001
* Reverted rL318911 since it broke the sanitizer-windows.Ying Yi2017-11-2319-437/+2
| | | | llvm-svn: 318914
* [lit] Implement non-pipelined ‘mkdir’, ‘diff’ and ‘rm’ commands ↵Ying Yi2017-11-2319-2/+437
| | | | | | | | | | | | | | | | | internally Summary: The internal shell already supports 'cd', ‘export’ and ‘echo’ commands. This patch adds implementation of non-pipelined ‘mkdir’, ‘diff’ and ‘rm’ commands as the internal shell builtins. Reviewers: Zachary Turner, Reid Kleckner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39567 llvm-svn: 318911
* Revert r318822 "[llvm-tblgen] - Stop using std::string in RecordKeeper."George Rimar2017-11-231-4/+5
| | | | | | It reported to have problems with memory sanitizers and DBUILD_SHARED_LIBS=ON. llvm-svn: 318899
* [llvm-tblgen] - Stop using std::string in RecordKeeper.George Rimar2017-11-221-5/+4
| | | | | | | | | | | RecordKeeper::getDef() is a hot place, it shows up in profiling and it creates std::string instance for each search in RecordMap though RecordKeeper::RecordMap can use StringRef as a key instead to avoid that. Patch do that change. Differential revision: https://reviews.llvm.org/D40170 llvm-svn: 318822
* [SelectionDAG] Add a isel matcher op to check the type of node results other ↵Craig Topper2017-11-221-5/+8
| | | | | | | | than result 0. I plan to use this to check the type of the mask result of masked gathers in the X86 backend. llvm-svn: 318820
* [TableGen] Improve error reportingEvandro Menezes2017-11-213-14/+19
| | | | | | | | | When searching for a resource unit, use the reference location instead of the definition location in case of an error. Differential revision: https://reviews.llvm.org/D40263 llvm-svn: 318803
* [Asm] Improve "too few operands" errorsOliver Stannard2017-11-211-1/+1
| | | | | | | | | | - We can still emit this error if the actual instruction has two or more operands missing compared to the expected one. - We should only emit this error once per instruction. Differential revision: https://reviews.llvm.org/D36746 llvm-svn: 318770
* [Asm] Finish matching once end of formal and actual lists reached (NFC)Oliver Stannard2017-11-211-0/+1
| | | | | | | | | | This is NFC, as the matcher would continue looping up to the maximum number of operands with no effect, but this should improve performance a bit, and makes the debug trace clearer. Differential revision: https://reviews.llvm.org/D36744 llvm-svn: 318769
* Revert r318759 due to make check-all failure on WindowsSander de Smalen2017-11-211-2/+3
| | | | llvm-svn: 318768
* [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-11-211-3/+2
| | | | | | | | | | | | | | | | | Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 318759
* Re-revert "Refactor debuginfo-tests."Zachary Turner2017-11-212-7/+4
| | | | | | | | | | This is still breaking greendragon. At this point I give up until someone can fix the greendragon bots, and I will probably abandon this effort in favor of using a private github repository. llvm-svn: 318722
* Resubmit "Refactor debuginfo-tests" again.Zachary Turner2017-11-202-4/+7
| | | | | | | | | | | | This was reverted due to the tests being run twice on some build bots. Each run had a slightly different configuration due to the way in which it was being invoked. This fixes the problem (albeit in a somewhat hacky way). Hopefully in the future we can get rid of the workflow of running debuginfo-tests as part of clang, and then this hack can go away. llvm-svn: 318697
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-2/+15
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 llvm-svn: 318650
* [LIT] Fix testing out-of-tree Clang buildsEric Fiselier2017-11-191-4/+4
| | | | | | | | | | | | | | | | | Summary: Currently, LIT configures the LLVM binary path before the Clang binary path. However this breaks testing out-of-tree Clang builds (where the LLVM binary path includes a copy of Clang). This patch reverses the order of the paths when looking for Clang, putting the Clang binary directory first. Reviewers: zturner, beanz, chapuni, modocache, EricWF Reviewed By: EricWF Subscribers: mgorny, cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D40217 llvm-svn: 318607
* [globalisel][tablegen] Generalize pointer-type inference by introducing ↵Daniel Sanders2017-11-183-4/+18
| | | | | | | | | | | | | | | ptypeN. NFC ptypeN is functionally the same as typeN except that it informs the SelectionDAG importer that an operand should be treated as a pointer even if it was written as iN. This is important for patterns that use iN instead of iPTR to represent pointers. E.g.: (set GPR64:$dst, (load GPR64:$addr)) Previously, this was handled as a hardcoded special case for the appropriate operands to G_LOAD and G_STORE. llvm-svn: 318574
* [lit] Try to improve Ctrl-C behavior on WindowsReid Kleckner2017-11-171-10/+10
| | | | | | | This functionality was broken during a refactor a while back because 'pool' is no longer in scope. llvm-svn: 318572
* Fix an issue with llvm lit tool substitutions.Zachary Turner2017-11-171-1/+1
| | | | | | | When using an installed clang with an in-tree llvm, we were not searching in the right paths for the tools. llvm-svn: 318564
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-172-2/+2
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Re-revert "Refactor debuginfo-tests"Zachary Turner2017-11-172-7/+4
| | | | | | | | | | | | | | | | | | | | | | This is still broken because it causes certain tests to be run twice with slightly different configurations, which is wrong in some cases. You can observe this by running: ninja -nv check-all | grep debuginfo-tests And seeing that it passes clang/test and clang/test/debuginfo-tests to lit, which causes it to run debuginfo-tests twice. The fix is going to involve either: a) figuring out that we're running in this "deprecated" configuration, and then deleting the clang/test/debuginfo-tests path, which should cause it to behave identically to before, or: b) make lit smart enough that it doesn't descend into a sub-suite if that sub-suite already has a lit.cfg file. llvm-svn: 318486
* Resubmit "Refactor debuginfo-tests"Zachary Turner2017-11-162-4/+7
| | | | | | | | | | This was reverted due to some failures on specific darwin buildbots, the issue being that the new lit configuration was not setting the SDKROOT environment variable. We've tested a fix locally and confirmed that it works, so this patch resubmits everything with the fix applied. llvm-svn: 318435
* [globalisel][tablegen] Generate rule coverage and use it to identify ↵Daniel Sanders2017-11-162-4/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
* [Docs] Add tablegen backend for target opcode documentationOliver Stannard2017-11-144-0/+240
| | | | | | | | | | This is a tablegen backend to generate documentation for the opcodes that exist for each target. For each opcode, it lists the assembly string, the names and types of all operands, and the flags and predicates that apply to the opcode. Differential revision: https://reviews.llvm.org/D31025 llvm-svn: 318155
* Revert "Update test_debuginfo.pl script to point to new tree location."Zachary Turner2017-11-132-7/+4
| | | | | | | | This reverts the aforementioned patch and 2 subsequent follow-ups, as some buildbots are still failing 2 tests because of it. Investigation is ongoing into the cause of the failures. llvm-svn: 318112
* [tablegen] Handle atomic predicates for ordering inside tablegen. NFC.Daniel Sanders2017-11-132-1/+64
| | | | | | | | | | | | | | | | Similar to r315841, GlobalISel and SelectionDAG require different code for the common atomic predicates due to differences in the representation. Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common atomic predicates related to ordering into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. llvm-svn: 318102
* [tablegen] Handle atomic predicates for memory type inside tablegen. NFC.Daniel Sanders2017-11-132-12/+33
| | | | | | | | | | | | | | | | Similar to r315841, GlobalISel and SelectionDAG require different code for the common atomic predicates due to differences in the representation. Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common atomic predicates related to memory type into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. llvm-svn: 318095
* [globalisel][tablegen] Add support for extload.Daniel Sanders2017-11-131-6/+12
| | | | llvm-svn: 318068
* fix printing of alias instructions by removing redundant spacingPetar Jovanovic2017-11-131-1/+3
| | | | | | | | | | | | Some alias instructions are printed with an extra space after the tab character. Fix this by skipping that space when the tab character is printed so that the instructions are aligned with the rest of the code. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35946 llvm-svn: 318059
* [globalisel][tablegen] Import signextload and zeroextload.Daniel Sanders2017-11-113-5/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. llvm-svn: 317971
* Update test_debuginfo.pl script to point to new tree location.Zachary Turner2017-11-101-1/+1
| | | | llvm-svn: 317949
* [debuginfo-tests] Make debuginfo-tests work in a standard configuration.Zachary Turner2017-11-101-3/+6
| | | | | | | | | | | | | | | | | | | Previously, debuginfo-tests was expected to be checked out into clang/test and then the tests would automatically run as part of check-clang. This is not a standard workflow for handling external projects, and it brings with it some serious drawbacks such as the inability to depend on things other than clang, which we will need going forward. The goal of this patch is to migrate towards a more standard workflow. To ease the transition for build bot maintainers, this patch tries not to break the existing workflow, but instead simply deprecate it to give maintainers a chance to update the build infrastructure. Differential Revision: https://reviews.llvm.org/D39605 llvm-svn: 317925
* Allow separation of declarations and definitions in <Target>ISelDAGToDAG.incKrzysztof Parzyszek2017-11-102-17/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to include the member function declarations in the instruction selector class separately from the member bodies. Defining GET_DAGISEL_DECL macro to any value will only include the member declarations. To include bodies, define GET_DAGISEL_BODY macro to be the selector class name. Example: class FooDAGToDAGISel : public SelectionDAGISel { // Pull in declarations only. #define GET_DAGISEL_DECL #include "FooISelDAGToDAG.inc" }; // Include the function bodies (with names qualified with the provided // class name). #define GET_DAGISEL_BODY FooDAGToDAGISel #include "FooISelDAGToDAG.inc" When neither of the two macros are defined, the function bodies are emitted inline (in the same way as before this patch). Differential Revision: https://reviews.llvm.org/D39596 llvm-svn: 317903
* [utils] Fix RISC-V support in update_llc_test_checks.pyAlex Bradbury2017-11-091-1/+1
| | | | | | scrub_asm_riscv now takes two arguments rather than one. llvm-svn: 317826
* [utils] Add RISC-V support to update_llc_test_checks.pyAlex Bradbury2017-11-081-0/+18
| | | | | | | | | | | | This should be a trivial change, and I've started using it for generating all tests at https://github.com/lowrisc/riscv-llvm (i.e. it's been tested in action quite a lot). Note that the regex does not attempt to match .cfi_startproc, as I want to ensure compatibility with functions that have the nounwind attribute. Differential Revision: https://reviews.llvm.org/D39789 llvm-svn: 317693
* Add a -D flag to FileCheck to define variablesAlexander Richardson2017-11-071-0/+7
| | | | | | | | | | | | | | | | Summary: This makes it very easy to test files that only differ in a constant value somewhere in the test case. Reviewers: jlebar, hfinkel, chandlerc, probinson Reviewed By: probinson Subscribers: probinson, llvm-commits Differential Revision: https://reviews.llvm.org/D39629 llvm-svn: 317572
* [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish ↵Florian Hahn2017-11-071-0/+5
| | | | | | | | | | | | | | | Scalable Vectors Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39087 llvm-svn: 317564
* update_mir_test_checks: Be careful about replacing entire vregsJustin Bogner2017-11-061-1/+2
| | | | | | | | | Previously, this could end up replacing a vreg like %14 with [[VREG1]]4, where VREG1 was the match for %1. That's obviously not correct, though it hasn't actually come up in any tests I've converted so far. llvm-svn: 317509
* Move the llvm-tblgen project into the Tablegenning folder on IDEs like ↵Aaron Ballman2017-11-041-0/+1
| | | | | | Visual Studio rather than leave it in the root directory. NFC. llvm-svn: 317420
* [X86] Teach EVEX->VEX pass to turn SHUFI32X4/SHUFF32X4/SHUFI64X/SHUFF64X2 ↵Craig Topper2017-11-041-0/+8
| | | | | | | | into VPERM2F128/VPERM2I128. This recovers some of the tests that were changed by r317403. llvm-svn: 317410
* [globalisel][tablegen] Skip src child predicatesDiana Picus2017-11-031-0/+3
| | | | | | | | | | | | | | | | | | The GlobalISel TableGen backend didn't check for predicates on the source children. This caused it to generate code for ARM patterns such as SMLABB or similar, but without properly checking for the sext_16_node part of the operands. This in turn meant that we would select SMLABB instead of MLA for simple sequences such as s32 + s32 * s32, which is wrong (we want a MLA on the full operands, not just their bottom 16 bits). This patch forces TableGen to skip patterns with predicates on the src children, so it doesn't generate code for SMLABB and other similar ARM instructions at all anymore. AArch64 and X86 are not affected. Differential Revision: https://reviews.llvm.org/D39554 llvm-svn: 317313
* [TableGen] Add an extra blank line to DAGISel output file to separate functions.Craig Topper2017-11-031-1/+1
| | | | llvm-svn: 317298
* [globalisel][regbank] Warn about MIR ambiguities when register bank/class ↵Daniel Sanders2017-11-011-0/+13
| | | | | | names clash. llvm-svn: 317132
* [X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit ↵Craig Topper2017-11-011-1/+7
| | | | | | | | | | VPALIGND/Q into VPALIGNR if the extended registers aren't being used. This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding. Differential Revision: https://reviews.llvm.org/D39401 llvm-svn: 317122
* [globalisel][tablegen] Add support for multi-insn emissionDaniel Sanders2017-11-011-9/+129
| | | | | | | | | | | | | | The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
* Fix warnings discovered by rL317076. [-Wunused-private-field]NAKAMURA Takumi2017-11-011-2/+1
| | | | llvm-svn: 317091
* [globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFCDaniel Sanders2017-11-011-23/+27
| | | | | | | The next commit will add support for multi-instruction emission so we need to start allocating instruction ID's instead of hard-coding them to 0. llvm-svn: 317057
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