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* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-17/+36
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-131-2/+3
| | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
* lit: Provide source locations in cfg files with older Python versionsAlp Toker2014-01-111-7/+8
| | | | | | | | | This commit prospectively brings the benefits of r198766 to older supported Python versions (2.5+). Tested with Python 2.6, 2.7, 3.1 and 3.3 (!) llvm-svn: 199009
* lit: execfile() isn't present in Python 3.3Alp Toker2014-01-111-9/+8
| | | | | | | | | | | | On the other hand, exec(compile()) doesn't work in older Python versions in the 2.x series. This commit introduces exec(compile()) with a fallback to plain exec(). That'll hopefully hit the sweet spot in terms of version support. Followup to r198766 which added enhanced source locations for lit cfg parsing. llvm-svn: 199006
* Constant propagate MachineInstrClassName.Roman Divacky2014-01-101-3/+1
| | | | llvm-svn: 198969
* All backends use MC now.Rafael Espindola2014-01-101-5/+1
| | | | llvm-svn: 198959
* Sink add_llvm_library(gtest_main) to UnitTestMain/CMakeLists.txt.NAKAMURA Takumi2014-01-102-3/+4
| | | | llvm-svn: 198933
* reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; ↵Kostya Serebryany2014-01-101-0/+7
| | | | | | this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off llvm-svn: 198922
* Revert "Disable LeakSanitizer in TableGen binaries, see PR18325"Alp Toker2014-01-091-7/+0
| | | | | | | | | | | To declare or define reserved identifers is undefined behaviour in standard C++. This needs to be addressed in compiler-rt before it can be used in LLVM. See the list discussion for details. This reverts commit r198858. llvm-svn: 198884
* Disable LeakSanitizer in TableGen binaries, see PR18325Kostya Serebryany2014-01-091-0/+7
| | | | llvm-svn: 198858
* lit: Provide file location in cfg error messagesAlp Toker2014-01-081-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Python doesn't do a good job at diagnosing string exec() so use execfile() where available. This should be a timesaver when trying to get to the bottom of build bot failures. Before: File "llvm/utils/lit/lit/TestingConfig.py", line 93, in load_from_path exec("exec data in cfg_globals") File "<string>", line 1, in <module> File "<string>", line 194, in <module> NameError: name 'typo' is not defined After: File "llvm/utils/lit/lit/TestingConfig.py", line 95, in load_from_path execfile(path, cfg_globals) File "clang/test/lit.cfg", line 194, in <module> typo ^~~~ NameError: name 'typo' is not defined llvm-svn: 198766
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-082-1/+6
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't ↵Craig Topper2014-01-062-9/+0
| | | | | | being used. llvm-svn: 198589
* Use patterns to remove some duplicate instructions.Craig Topper2014-01-051-3/+1
| | | | llvm-svn: 198550
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-051-2/+1
| | | | llvm-svn: 198547
* Remove no longer needed x86 disassembler hack.Craig Topper2014-01-051-6/+0
| | | | llvm-svn: 198546
* Mark x86 _alt instructions as AsmParserOnly so they will be omitted from ↵Craig Topper2014-01-051-2/+1
| | | | | | disassembler without string matches. llvm-svn: 198545
* Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode ↵Craig Topper2014-01-051-3/+1
| | | | | | and remove disassmbler table emitter hack. llvm-svn: 198544
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-052-2/+5
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-051-3/+0
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
* Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. ↵Craig Topper2014-01-051-3/+4
| | | | | | Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time. llvm-svn: 198529
* Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. ↵Craig Topper2014-01-041-2/+1
| | | | | | Remove disassembler hack. llvm-svn: 198515
* Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it ↵Craig Topper2014-01-041-2/+1
| | | | | | won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. llvm-svn: 198475
* FileCheck: Print a nice error message for missing closing ']' in regex vars.Adrian Prantl2014-01-031-4/+9
| | | | llvm-svn: 198449
* [TableGen] Handle ValueType in CodeGenDAGPatterns GetNumNodeResultsHal Finkel2014-01-021-0/+3
| | | | | | | | | | | | A ValueType in a pattern dag is a type cast, and GetNumNodeResults should handle it (the type cast has only one result). This comes up, for example, during the type checking of pattern fragments, for example, AArch64's Neon_combine_2d fragment is: dag Operands = (ops node:$Rm, node:$Rn); dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn))); llvm-svn: 198347
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-021-1/+0
| | | | llvm-svn: 198336
* Remove unused HasFROperands field from disassembler.Craig Topper2014-01-022-17/+0
| | | | llvm-svn: 198332
* Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack ↵Craig Topper2014-01-021-4/+0
| | | | | | from the disassembler table builder. llvm-svn: 198327
* Remove unnecessary stirng comparison from disassembler.Craig Topper2014-01-021-1/+0
| | | | llvm-svn: 198325
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-021-4/+0
| | | | | | table builder doesn't need to string match them to exclude them. llvm-svn: 198323
* Remove unused function argument.Craig Topper2014-01-022-5/+3
| | | | llvm-svn: 198291
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-013-28/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-011-8/+4
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-012-43/+50
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-013-51/+25
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-313-25/+51
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-303-51/+25
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* Remove EscapeFilter. It's funcionality can be covered by correctly using ↵Craig Topper2013-12-303-33/+15
| | | | | | ExtendedFilter and ExactFilter. No functional change. llvm-svn: 198226
* Simplify filter accepts function to just return 'condition' instead of ↵Craig Topper2013-12-301-28/+13
| | | | | | branching to return true/false. No functional change. llvm-svn: 198221
* [CMake] Generate ${BUILD_MODE}/llvm-lit for each ${CMAKE_CONFIGURATION_TYPES}.NAKAMURA Takumi2013-12-302-5/+17
| | | | | | | | | | | | llvm-lit can be invoked; $ Release/bin/llvm-lit instead of; $ bin/llvm-lit --param buid_mode=Release llvm-svn: 198206
* Python compatibility fix for r198150Alp Toker2013-12-291-8/+5
| | | | | | | | Remove the stat call error reporting for now. It wasn't essential so silent fallback should be fine here. llvm-svn: 198155
* Prospective Python 3 fix for r198150Alp Toker2013-12-291-1/+1
| | | | llvm-svn: 198152
* lit: Incremental test schedulingAlp Toker2013-12-293-2/+36
| | | | | | | | | | | | | | | | Add option -i to prioritize test runs by source file modification time and previous failure state. This optimal scheduling reduces typical test-and-fix iteration times to a matter of seconds by rapidly answering the questions: 1) Did my recent change fix tests that were previously failing? 2) Do the tests I just wrote / modified still work? The current implementation requires write permissions to the source tree because it uses mtimes to track failures. llvm-svn: 198150
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-251-4/+26
| | | | llvm-svn: 198013
* Install three utils, "FileCheck", "count", and "not", for now to appease ↵NAKAMURA Takumi2013-12-203-6/+6
| | | | | | | | | | llvmlab dragonegg builder. Since r197684, "install/bin/llvm-config --obj-root" hasn't shown the build tree. The builder was finding utils in the build tree, from the installed tree. I will revert this after dragonegg builder would be tweaked not to use installed llvm-config. llvm-svn: 197786
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-2/+3
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* Add support for positionally-encoded operands to FixedLenDecoderEmitterHal Finkel2013-12-191-4/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, the PowerPC instruction definitions make heavy use of the positional operand encoding heuristic to map operands onto bitfield variables in the instruction definitions. Changing this to use name-based mapping is not trivial, however, because additional infrastructure needs to be designed to handle mapping of complex operands (with multiple suboperands) onto multiple bitfield variables. In the mean time, this adds support for positionally encoded operands to FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC backend. To prevent an accidental reliance on this feature, and to prevent an undesirable interaction with existing disassemblers, a backend must opt-in to this support by setting the new decodePositionallyEncodedOperands instruction-set bit to true. When enabled, this iterates the variables that contribute to the instruction encoding, just as the encoder does, and emulates the procedure the encoder uses to map "numbered" operands to variables. The bit range for each variable is also determined as the encoder determines them. This map is then consulted during the decoder-generator's loop over operands to decode, allowing the decoder to understand both position-based and name-based operand-to-variable mappings. As noted in the comment on the decodePositionallyEncodedOperands definition, this support should be removed once it is no longer needed. There should be no change to existing disassemblers. llvm-svn: 197691
* Add support for PointerLikeRegClass to FixedLenDecoderEmitterHal Finkel2013-12-191-0/+4
| | | | | | | | This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter should recognize PointerLikeRegClass operands as register types, and generate register-like decoding calls instead of treating them like immediates. llvm-svn: 197680
* Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel2013-12-174-37/+47
| | | | | | | | | | | | | | | The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
* Tweak lit/TestingConfig.py Py3-compatible. has_key is dead.NAKAMURA Takumi2013-12-171-1/+1
| | | | llvm-svn: 197462
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