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* Formatting. No functional change.Chad Rosier2012-08-211-2/+2
| | | | llvm-svn: 162292
* Add stub methods for mips assembly matcher. Akira Hatanaka2012-08-171-1/+3
| | | | | | Patch by Vladimir Medic. llvm-svn: 162124
* Declare some for loop indices inside the for loop statement.Craig Topper2012-08-171-20/+13
| | | | llvm-svn: 162085
* Fix up indentation of outputted decode function for readability.Craig Topper2012-08-171-8/+8
| | | | llvm-svn: 162082
* lit: Show actually created count of threads. The incorrect threads count is ↵NAKAMURA Takumi2012-08-171-3/+3
| | | | | | | | printed if the number of tests are less than the number of default threads. Thanks to Vinson Lee, reported in PR13620. llvm-svn: 162078
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-163-0/+3
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
* Add a CoveringSubRegIndices field to SubRegIndex records.Jakob Stoklund Olesen2012-08-151-9/+22
| | | | | | | This can be used to tell TableGen to use a specific SubRegIndex instead of synthesizing one when discovering all sub-registers. llvm-svn: 161982
* Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen2012-08-153-33/+30
| | | | | | | | | | | TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. llvm-svn: 161964
* Fix a const violation in the generated disassembler.Benjamin Kramer2012-08-151-2/+2
| | | | llvm-svn: 161940
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-281/+722
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Add some missing includes for the build against stdcxx.Joerg Sonnenberger2012-08-101-0/+1
| | | | llvm-svn: 161657
* Use the final .version number for LLVM_MINOR_VERSION in Apple llvmCore builds.Bob Wilson2012-08-101-1/+1
| | | | | | | | We've switched to a 3-component version numbering scheme for Apple releases, and with this scheme, the final number is the one most relevant for setting LLVM_MINOR_VERSION. <rdar://problem/12071459> llvm-svn: 161645
* [ms-inline asm] Add a new Inline Asm Non-Standard Dialect attribute.Chad Rosier2012-08-101-0/+1
| | | | | | | | | | | | | | This new attribute is intended to be used by the backend to determine how the inline asm string should be parsed/printed. This patch adds the ia_nsdialect attribute and also adds a test case to ensure the IR is correctly parsed, but there is no functional change at this time. The standard dialect is assumed to be AT&T. Therefore, this attribute should only be added to MS-style inline assembly statements, which use the Intel dialect. If we ever support more dialects we'll need to add additional state to the attribute. llvm-svn: 161641
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-081-0/+1
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. llvm-svn: 161471
* Remove extraneous ';'.Bill Wendling2012-08-041-1/+1
| | | | llvm-svn: 161298
* Remove redundant '== true' after a comparison.Richard Trieu2012-08-021-1/+1
| | | | llvm-svn: 161223
* [yaml2obj] Fix build. Apparently I've gotten too familiar with C++11.Michael J. Spencer2012-08-021-1/+1
| | | | llvm-svn: 161206
* Add yaml2obj. A utility to convert YAML to binaries.Michael J. Spencer2012-08-024-1/+905
| | | | | | | | yaml2obj takes a textual description of an object file in YAML format and outputs the binary equivalent. This greatly simplifies writing tests that take binary object files as input. llvm-svn: 161205
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-012-29/+54
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* [obj2yaml] Print the Relocations header.Michael J. Spencer2012-07-311-1/+2
| | | | llvm-svn: 161082
* Use regex instead of special casing clang and llvm libraries.Ted Kremenek2012-07-311-2/+1
| | | | llvm-svn: 161065
* Use uint8_t to store the InstructionContext table. Saves 768 bytes of static ↵Craig Topper2012-07-311-1/+1
| | | | | | data. llvm-svn: 161034
* Tidy up. Move for loop index declarations into for statements. Use unsigned ↵Craig Topper2012-07-311-39/+26
| | | | | | instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent. llvm-svn: 161033
* Tidy up function argument formatting.Craig Topper2012-07-311-35/+17
| | | | llvm-svn: 161032
* Remove trailing whitespaceCraig Topper2012-07-311-25/+25
| | | | llvm-svn: 161031
* Remove trailing whitespaceCraig Topper2012-07-311-31/+31
| | | | llvm-svn: 161030
* Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The ↵Craig Topper2012-07-301-2/+1
| | | | | | isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. llvm-svn: 160951
* Remove some unnecessary filter checks. They were already covered by ↵Craig Topper2012-07-301-12/+0
| | | | | | IsCodeGenOnly llvm-svn: 160950
* Remove check for sub class of X86Inst from filter function since caller ↵Craig Topper2012-07-301-6/+2
| | | | | | guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already. llvm-svn: 160949
* Simplify code that filtered certain instructions in two different ways. No ↵Craig Topper2012-07-301-14/+1
| | | | | | functional change. llvm-svn: 160948
* Remove check for f256mem from has256BitOperands as nothing depended on it ↵Craig Topper2012-07-301-1/+1
| | | | | | and it isn't the only 256-bit memory type anyway. llvm-svn: 160946
* Remove trailing whitespace.Craig Topper2012-07-301-85/+85
| | | | llvm-svn: 160945
* Clean up includes.Craig Topper2012-07-271-1/+1
| | | | llvm-svn: 160852
* Eliminate the large XXXSubRegTable constant arrays.Jakob Stoklund Olesen2012-07-271-53/+31
| | | | | | | | | | | These tables were indexed by [register][subreg index] which made them, very large and sparse. Replace them with lists of sub-register indexes that match the existing lists of sub-registers. MCRI::getSubReg() becomes a very short linear search, like getSubRegIndex() already was. llvm-svn: 160843
* Remove support for 'CompositeIndices' and sub-register cycles.Jakob Stoklund Olesen2012-07-261-52/+19
| | | | | | | | | | | | Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone, there is no longer a need for the CompositeIndices construct in .td files. Sub-register index composition can be specified on the SubRegIndex itself using the ComposedOf field. Also enforce unique names for sub-registers in TableGen. The same sub-register cannot be available with multiple sub-register indexes. llvm-svn: 160842
* Make l/q suffixes on AVX forms of scalar convert instructions consistent ↵Craig Topper2012-07-261-2/+1
| | | | | | with their non-AVX forms. llvm-svn: 160775
* Differentially encode all MC register lists.Jakob Stoklund Olesen2012-07-251-44/+30
| | | | | | | This simplifies MCRegisterInfo and shrinks the target descriptions a bit more. llvm-svn: 160758
* Fix a "Bad fd number" error on some platforms due to a less portableEric Christopher2012-07-231-1/+1
| | | | | | | | redirection in the system call. Patch by Andy Gibbs. llvm-svn: 160644
* Fix a typo (the the => the)Sylvestre Ledru2012-07-234-4/+4
| | | | llvm-svn: 160621
* lit: Use close_fds=True on UNIX, to avoid file descriptor pollution ofDaniel Dunbar2012-07-201-1/+5
| | | | | | subprocesses. llvm-svn: 160556
* Move around some enum elements so that lastMRM corrects gets assigned 56, whichRichard Trieu2012-07-181-2/+2
| | | | | | | is one more that MRM_DF which is 55. Previously, it held value 45, the same as MRM_D0. llvm-svn: 160465
* TblGen: Tweak to pretty-print DAGISel.inc a bit better.Jim Grosbach2012-07-181-2/+2
| | | | llvm-svn: 160463
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-182-6/+13
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* TableGen: Pattern<> references to null_frag are a nop.Jim Grosbach2012-07-171-0/+5
| | | | | | | | A standalone pattern defined in a multiclass expansion should handle null_frag references just like patterns on instructions. Follow-up to r160333. llvm-svn: 160384
* TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach2012-07-171-2/+36
| | | | | | | | | | | | | | | | | | | Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; llvm-svn: 160333
* Defer checking for registers in the MC AsmMatcher until the after ↵Owen Anderson2012-07-161-16/+16
| | | | | | user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class. llvm-svn: 160327
* TableGen: Assembly matcher 'insufficient operands' diagnostic.Jim Grosbach2012-07-121-0/+1
| | | | | | | | | | Make sure the tblgen'erated asm matcher correctly returns numoperands+1 as the ErrorInfo when the problem was that there weren't enough operands specified. rdar://9142751 llvm-svn: 160144
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-122-14/+14
| | | | | | myself and Manman Ren. llvm-svn: 160110
* Machine model: allow itineraries to be shared by different processor models.Andrew Trick2012-07-091-0/+12
| | | | llvm-svn: 159959
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-077-229/+508
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
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