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* Add an operator for vmull_lane so it can be implemented without a clang builtin.Bob Wilson2010-12-072-0/+7
| | | | llvm-svn: 121187
* Handle recursive values. Add comments.Devang Patel2010-12-071-23/+53
| | | | llvm-svn: 121184
* Remove reference to the CMPz instruction patterns for ARM.Jim Grosbach2010-12-071-8/+1
| | | | llvm-svn: 121180
* Add new built-in operations for vmull and vmull_nBob Wilson2010-12-072-0/+22
| | | | | | | so they can be implemented without requiring clang builtins. Radar 8446238. llvm-svn: 121173
* Trailing whitespace.Jim Grosbach2010-12-071-29/+29
| | | | llvm-svn: 121167
* Change assert to diagnostic. Message still needs work, but it's better thanJim Grosbach2010-12-071-3/+9
| | | | | | an assert, at least. llvm-svn: 121166
* utils/lit/lit/TestFormats.py: [PR8438] unittests: Seek *Tests (not ↵NAKAMURA Takumi2010-12-071-2/+3
| | | | | | BUILD_MODE/*Tests) under whole unittests/ if BUILD_MODE == '.' llvm-svn: 121118
* Add an OpReinterpret operation to TableGen's NeonEmitter.Bob Wilson2010-12-072-40/+73
| | | | | | | | An OpReinterpret entry is handled by translating it to OpCast intrinsics for all combinations of source and destination types with the same total size. This will be used to generate all the vreinterpret intrinsics. llvm-svn: 121087
* Fix whitespace.Bob Wilson2010-12-071-5/+5
| | | | llvm-svn: 121086
* Add python scripts to extract debug info using LLDB and do comparison.Devang Patel2010-12-072-0/+207
| | | | llvm-svn: 121079
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-061-0/+1
| | | | llvm-svn: 121072
* KillTheDoctor: Cleanup error_code usage.Michael J. Spencer2010-12-061-18/+14
| | | | llvm-svn: 120986
* KillTheDoctor: Fix spelling.Michael J. Spencer2010-12-061-6/+6
| | | | llvm-svn: 120985
* Remove trailing whitespace.Bob Wilson2010-12-042-112/+112
| | | | llvm-svn: 120891
* Get Neon intrinsic names from the new "Name" field in the tblgen recordsBob Wilson2010-12-031-4/+4
| | | | | | instead of just converting the record name to lowercase. llvm-svn: 120809
* I did it wrong. Don't disregard these encodings here.Bill Wendling2010-12-031-7/+0
| | | | llvm-svn: 120786
* Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gprBill Wendling2010-12-031-0/+7
| | | | | | instructions. They are handled as special moves, but encoded as a normal move. llvm-svn: 120779
* Add support for "_lane" variants of VMUL, VMLA, and VMLS Neon intrinsics.Bob Wilson2010-12-032-0/+24
| | | | llvm-svn: 120764
* Support using macros for Neon intrinsics implemented without builtins.Bob Wilson2010-12-031-49/+58
| | | | | | | | Intrinsics implemented with Clang builtins could already be implemented as either inline functions or macros, but intrinsics implemented directly (without builtins) could only be inline functions. llvm-svn: 120763
* Simplify code in Neon intrinsics. No functional changes intended.Bob Wilson2010-12-021-43/+37
| | | | | | | For most intrinsics, there is no need to allocate a temporary to hold the result value; just return it directly. llvm-svn: 120695
* Assign arguments of Neon intrinsic macros to local temporaries.Bob Wilson2010-12-021-4/+31
| | | | | | | | Since we're casting them for the calls to the builtins, we need this to make sure their types get checked in the same way they would if the intrinsics were implemented as inline functions. llvm-svn: 120693
* Use statement expressions in Neon intrinsics defined as macros.Bob Wilson2010-12-021-9/+8
| | | | | | | This is in preparation for adding assignments to temporaries to ensure that the proper type checking is done. llvm-svn: 120649
* Add casts for splatted scalars in calls to Neon builtins.Bob Wilson2010-12-021-5/+5
| | | | llvm-svn: 120641
* Add a missing cast for Neon vsbl results.Bob Wilson2010-12-021-2/+3
| | | | | | | The bitwise operations are always done with unsigned values, but the result may be signed. llvm-svn: 120640
* Add another missing cast for Neon vcombine results.Bob Wilson2010-12-021-1/+1
| | | | llvm-svn: 120639
* Add casts in arm_neon.h for result values in inline functions as well as macros.Bob Wilson2010-12-021-1/+1
| | | | | | We should not rely on lax-vector-conversions for these intrinsics to work. llvm-svn: 120638
* Avoid "char" for Neon vector elements; make it explicitly signed (or unsigned).Bob Wilson2010-12-021-5/+7
| | | | llvm-svn: 120632
* Cast scalar results of Neon macros to the correct type.Bob Wilson2010-12-021-1/+1
| | | | llvm-svn: 120631
* Add explicit casts for vector arguments to Neon builtins.Bob Wilson2010-12-011-5/+31
| | | | | | This avoids warnings with -Wvector-conversions. Radar 8228022. llvm-svn: 120597
* Add some comments for TableGen's NeonEmitter.Bob Wilson2010-12-012-11/+16
| | | | llvm-svn: 120596
* Cleanup: simplify checks for integers between 2 and 4.Bob Wilson2010-12-011-4/+4
| | | | llvm-svn: 120595
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-011-0/+1
| | | | | | | instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson2010-11-301-2/+0
| | | | | | | | | This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-301-0/+2
| | | | llvm-svn: 120449
* The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,Jim Grosbach2010-11-301-5/+0
| | | | | | | no extra encoding information), so we no longer need to special case them here. llvm-svn: 120444
* Tidy up.Jim Grosbach2010-11-301-2/+3
| | | | llvm-svn: 120443
* Delete a few no longer needed references to pseudos.Jim Grosbach2010-11-301-4/+0
| | | | llvm-svn: 120441
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-301-0/+1
| | | | | | | | The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-291-6/+1
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-1/+1
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* I swear I did a make clean and make before committing all this...Michael J. Spencer2010-11-295-5/+5
| | | | llvm-svn: 120304
* Missed another one.Michael J. Spencer2010-11-291-1/+1
| | | | llvm-svn: 120302
* Merge System into Support.Michael J. Spencer2010-11-2917-27/+27
| | | | llvm-svn: 120298
* Fix copy-and-paste error in exception message.Bob Wilson2010-11-231-1/+1
| | | | llvm-svn: 120033
* lit.GoogleTest: On case-insensitive filesystem, matching should be ↵NAKAMURA Takumi2010-11-191-2/+2
| | | | | | | | case-insensitive when directory name is checked with test_sub_dir. On MSVS8, ${CMAKE_CFG_INTDIR}, aka $(OutDir), has capitalized name(eg. Debug), although $(OutDir) is made with lower case(eg. debug). llvm-svn: 119781
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim2010-11-181-0/+1
| | | | | | | | | .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. llvm-svn: 119760
* Give the exclamation point a name instead of a number.Bill Wendling2010-11-181-0/+1
| | | | llvm-svn: 119759
* Change the 'x' type modifier for Neon intrinsics to force a signed integer.Bob Wilson2010-11-181-0/+5
| | | | | | | | This makes it symmetric with the 'u' modifier that forces an unsigned type. This is needed for unsigned vector shifts, where the shift amount still needs to be signed. PR8482 (Radar 8603521). llvm-svn: 119742
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-173-0/+3
| | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-171-0/+4
| | | | | | | | | instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
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