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* Sort the #include lines for utils/...Chandler Carruth2012-12-0430-63/+54
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Add an MCPhysReg typedef to replace naked uint16_t.Jakob Stoklund Olesen2012-11-291-7/+7
| | | | | | Use this type for arrays of physical registers. llvm-svn: 168850
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-2/+2
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* Make the AttrListPtr object a part of the LLVMContext.Bill Wendling2012-11-201-1/+1
| | | | | | | | | When code deletes the context, the AttributeImpls that the AttrListPtr points to are now invalid. Therefore, instead of keeping a separate managed static for the AttrListPtrs that's reference counted, move it into the LLVMContext and delete it when deleting the AttributeImpls. llvm-svn: 168354
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-0/+1
| | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
* Fix issue with invalid flat operand numberEvandro Menezes2012-11-091-3/+1
| | | | | | | Avoid iterating over list of operands beyond the number of operands in it. PS: this fixes issue with revision #167634. llvm-svn: 167635
* Fix issue with invalid flat operand numberEvandro Menezes2012-11-091-1/+6
| | | | | | Avoid iterating over list of operands beyond the number of operands in it. llvm-svn: 167634
* Add support of RTM from TSX extensionMichael Liao2012-11-081-8/+9
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* Fix a build problem with xlc. The error message wasRafael Espindola2012-11-022-2/+2
| | | | | | | | | "../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+". "../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate. Patch by Kai. llvm-svn: 167311
* Generate a table-driven version of TRI::composeSubRegIndices().Jakob Stoklund Olesen2012-11-011-26/+102
| | | | | | | | | | Explicitly allow composition of null sub-register indices, and handle that common case in an inlinable stub. Use a compressed table implementation instead of the previous nested switches which generated pretty bad code. llvm-svn: 167190
* Don't return false when the function's return type is a pointer.Kaelyn Uhrain2012-10-251-2/+2
| | | | llvm-svn: 166719
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-2526-305/+375
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Remove unused member & unnecessary semicolon.David Blaikie2012-10-251-3/+2
| | | | llvm-svn: 166694
* llvm/utils/TableGen/CMakeLists.txt: Update corresponding to r166685.NAKAMURA Takumi2012-10-251-0/+1
| | | | llvm-svn: 166686
* add TableGen support to create relationship maps between instructionsSebastian Pop2012-10-253-0/+612
| | | | | | | | | | | Relationship maps are represented as InstrMapping records which are parsed by TableGen and the information is used to construct mapping tables to represent appropriate relations between instructions. These tables are emitted into XXXGenInstrInfo.inc file along with the functions to query them. Patch by Jyotsna Verma <jverma@codeaurora.org>. llvm-svn: 166685
* Don't use stack unwinding to provide the location information forJoerg Sonnenberger2012-10-244-69/+77
| | | | | | SetTheory, but pass down the location explicitly. llvm-svn: 166629
* Allow the commuted form of tied-operand constraints in tablegen ("$dst = $src",Lang Hames2012-10-201-5/+6
| | | | | | rather than "$src = $dst"). llvm-svn: 166382
* Add an enum for the return and function indexes into the AttrListPtr object. ↵Bill Wendling2012-10-151-2/+2
| | | | | | This gets rid of some magic numbers. llvm-svn: 165924
* Attributes RewriteBill Wendling2012-10-151-4/+4
| | | | | | | | | | Convert the internal representation of the Attributes class into a pointer to an opaque object that's uniqued by and stored in the LLVMContext object. The Attributes class then becomes a thin wrapper around this opaque object. Eventually, the internal representation will be expanded to include attributes that represent code generation options, etc. llvm-svn: 165917
* [ms-inline asm] Use the new API introduced in r165830 in lieu of theChad Rosier2012-10-121-22/+15
| | | | | | MapAndConstraints vector. Also remove the unused Kind argument. llvm-svn: 165833
* Change (!list.size() == 0) to (!list.empty()). No functional change.Richard Trieu2012-10-121-1/+1
| | | | llvm-svn: 165812
* Remove unnecessary classof()'sSean Silva2012-10-111-2/+0
| | | | | | | isa<> et al. automatically infer when the cast is an upcast (including a self-cast), so these are no longer necessary. llvm-svn: 165767
* Remove extra semicolons.Chad Rosier2012-10-111-2/+2
| | | | llvm-svn: 165757
* tblgen: Compile TableGen without RTTI.Sean Silva2012-10-102-2/+0
| | | | | | TableGen no longer needs RTTI! llvm-svn: 165651
* tblgen: Move mini Type hierarchy to LLVM-style RTTI.Sean Silva2012-10-101-4/+22
| | | | llvm-svn: 165648
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-109-42/+36
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-1013-98/+98
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Pass into the AttributeWithIndex::get method an ArrayRef of attributeBill Wendling2012-10-101-35/+27
| | | | | | enums. These are then created via the correct Attributes creation method. llvm-svn: 165607
* TableGen subtarget emitter cleanup.Andrew Trick2012-10-102-29/+39
| | | | | | Consistently evaluate Aliases and Sequences recursively. llvm-svn: 165604
* misched: Generate IsBuffered flag for machine resources.Andrew Trick2012-10-101-4/+4
| | | | llvm-svn: 165602
* Move TargetData to DataLayout.Micah Villmow2012-10-081-2/+2
| | | | llvm-svn: 165403
* [ms-inline asm] Add a few typedefs to simplify future changes.Chad Rosier2012-10-051-11/+12
| | | | llvm-svn: 165324
* tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.Sean Silva2012-10-051-1/+1
| | | | | | | | This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of these uses are actually more like isa<> or cast<>, and will be changed to the semanticaly appropriate one in a future patch. llvm-svn: 165291
* Added instregex support to TableGen subtarget emitter.Andrew Trick2012-10-033-10/+84
| | | | | | | | This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. llvm-svn: 165180
* TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick2012-10-033-130/+229
| | | | | | | | | A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. llvm-svn: 165179
* Cleanup TableGen subtarget emitter.Andrew Trick2012-10-032-6/+7
| | | | llvm-svn: 165178
* [ms-inline asm] Default to the 'm' constraint. This matches the behavior of theChad Rosier2012-10-031-3/+3
| | | | | | MSVC compiler. llvm-svn: 165174
* tblgen: Migrate llvm-tblgen to new TableGenMain API.Sean Silva2012-10-031-82/+77
| | | | llvm-svn: 165166
* Fix 80-column violations. Cleanup whitespace in generated code.Chad Rosier2012-10-021-15/+23
| | | | llvm-svn: 164983
* [ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier2012-10-011-45/+38
| | | | | | | | | | | map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. llvm-svn: 164979
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-272-2/+2
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-272-2/+2
| | | | llvm-svn: 164767
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-6/+6
| | | | | | Also remove an unused argument. llvm-svn: 164567
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-2/+2
| | | | llvm-svn: 164548
* Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick2012-09-223-87/+295
| | | | | | | Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. llvm-svn: 164451
* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-211-2/+2
| | | | llvm-svn: 164420
* Whitespace.Chad Rosier2012-09-211-2/+2
| | | | llvm-svn: 164406
* Add in new data types that are used by AMDIL/ANL among others.Micah Villmow2012-09-191-0/+8
| | | | llvm-svn: 164261
* Soften the pattern-can-never-match error in TableGen into a warning. This ↵Owen Anderson2012-09-191-2/+5
| | | | | | pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). llvm-svn: 164256
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-192-19/+2
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
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