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* Revert r317040: [globalisel][tablegen] Keep track of the insertion point ↵Daniel Sanders2017-10-311-77/+33
| | | | | | | | | | while adding BuildMIAction's. NFC The same bots fail but I believe I know what the issue is now. These bots are missing the const_iterator versions of insert/emplace/etc. that were introduced in C++11. llvm-svn: 317042
* Re-commit: [globalisel][tablegen] Keep track of the insertion point while ↵Daniel Sanders2017-10-311-33/+77
| | | | | | | | | | | | | | | | | | | adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots didn't like a call to emplace(). I've replaced it with insert() to see if it's a quirk of the C++11 support. llvm-svn: 317040
* Revert r317029: [globalisel][tablegen] Keep track of the insertion point ↵Daniel Sanders2017-10-311-77/+33
| | | | | | | | while adding BuildMIAction's. NFC The Linux bots don't seem to like this usage of emplace(). Reverting while I look into it. llvm-svn: 317033
* [globalisel][tablegen] Keep track of the insertion point while adding ↵Daniel Sanders2017-10-311-33/+77
| | | | | | | | | | | | | | | BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. llvm-svn: 317029
* [globalisel][tablegen] Factor out implicit def/use renderers from ↵Daniel Sanders2017-10-311-12/+48
| | | | | | | | | | | | createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
* [globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction ↵Daniel Sanders2017-10-311-43/+73
| | | | | | | | | | | | | | | | | | to choose a mutatable instruction. NFC Prepare for multiple instruction emission by allowing BuildMIAction to search for a suitable matcher that will support mutation. This patch deliberately neglects to add matchers aside from the root to preserve NFC. That said, it should be noted that until we support mutations other than just the opcode the chances of finding a non-root instruction for which canMutate() is true, is essentially zero. Furthermore in the presence of multi-instruction emission the chances of finding any instruction for which canMutate() is true is also zero. Nevertheless, we can't continue to require that all BuildMIAction's consider the root of the match to be recyclable due to the risk of recycling it twice in the same rule. llvm-svn: 317022
* [globalisel][tablegen] Allow any comment in DebugCommentAction. NFCDaniel Sanders2017-10-311-6/+6
| | | | llvm-svn: 317017
* [TableGen] Use Twine instead of std::string concatenation in two calls to ↵Craig Topper2017-10-261-4/+4
| | | | | | PrintFatalError. llvm-svn: 316697
* [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell ↵Craig Topper2017-10-261-5/+15
| | | | | | | | check function so it can use the correct table based on variant. I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants. llvm-svn: 316641
* [AsmParser][TableGen] Make the generated mnemonic spell checker function a ↵Craig Topper2017-10-261-3/+9
| | | | | | | | file local static function. Also only emit in targets that specificially request it. This is required so we don't get an unused static function error. llvm-svn: 316640
* [globalisel][tablegen] Fix future undefined behaviour in r316463.Daniel Sanders2017-10-241-1/+4
| | | | | | | I missed a dereference of `Matched` that preceeded the new check. Thanks to Justin Bogner for spotting it. llvm-svn: 316480
* [globalisel][tablegen] Multi-insn emission requires that BuildMIAction ↵Daniel Sanders2017-10-241-6/+6
| | | | | | | | | | | support not being linked to an InstructionMatcher. NFC When multi-instruction emission is supported, it will no longer be guaranteed that every BuildMIAction has a corresponding matched instruction. BuildMIAction should support not having one to cover the case where a rule produces more instructions than it matched. llvm-svn: 316463
* [TableGen] Fix some formatting quirks in the subtarget output file.Craig Topper2017-10-241-4/+5
| | | | llvm-svn: 316450
* [TableGen] Simplify some of the subtarget emission by removing code that ↵Craig Topper2017-10-241-45/+11
| | | | | | | | avoids printing commas at the end of arrays and enums. The C++ standard allows for trailing commas. We already do this in many other emitters. llvm-svn: 316449
* [globalisel][tablegen] Remove unused InstructionMatcher's. NFCDaniel Sanders2017-10-241-25/+12
| | | | llvm-svn: 316407
* [globalisel][tablegen] Import stores and allow GISel to automatically ↵Daniel Sanders2017-10-231-1/+79
| | | | | | | | | | | | | | | | | substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
* [X86] Fix disassembler table generation to prevent instructions tagged with ↵Craig Topper2017-10-233-16/+20
| | | | | | 'PS' being inherited into PD/XS/XD attribute entries. llvm-svn: 316345
* [X86] Update a doxygen comment in the disassembler tablegen code. NFCCraig Topper2017-10-231-0/+1
| | | | llvm-svn: 316309
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-233-57/+161
| | | | | | Fixes PR31955. llvm-svn: 316308
* [X86] More correctly support LIG and WIG for EVEX instructions in the ↵Craig Topper2017-10-221-74/+168
| | | | | | | | | | disassembler tables. This is similar to how we generate the VEX tables. More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding). llvm-svn: 316294
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-223-16/+21
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-211-13/+13
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-7/+7
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* Revert MSVC 2017 build fix and fix it by moving the method that implicitly ↵Reid Kleckner2017-10-161-32/+34
| | | | | | instantiates addPredicate out of line llvm-svn: 315932
* Fix the build of GlobalISelEmitter with MSVC 2017 by specializing earlierReid Kleckner2017-10-161-12/+12
| | | | | | | MSVC doesn't seem to like implicitly instantiating addPredicate and then explicitly specializing it later. It causes an internal compiler error. llvm-svn: 315930
* [TableGen] Simplify CallingConvEmitter.cpp. NFC.Javed Absar2017-10-161-8/+8
| | | | llvm-svn: 315911
* [TableGen] Range loopify DAGISelMatcher. NFC.Javed Absar2017-10-161-15/+15
| | | | llvm-svn: 315891
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-13/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-11/+5
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-161-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* [globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders2017-10-161-17/+105
| | | | | | | | | | | | | | | | | | | | | | | | MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
* [tablegen] Use hasPredCode()/hasImmCode() instead of ↵Daniel Sanders2017-10-152-5/+17
| | | | | | | | getPredCode().empty()/getImmCode().empty(). NFC These are cheaper ways of testing for the presence of code than generating the C++ code and testing it's empty. llvm-svn: 315872
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-151-31/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-151-99/+31
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-151-31/+99
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* [TableGen] Remove error checks incorrectly failing on non-error conditionsKrzysztof Parzyszek2017-10-151-49/+6
| | | | | | | | | | | | | In type inference, an empty type set for a specific hw mode is not an error. In earlier stages of the design it was, but having to use non- parameterized types with target intrinsics necessarily led to type contradictions: since the intrinsics used specific types, they were only valid for a specific hw mode, and the resulting type set for other modes ended up empty. To accommodate the existence of such intrinsics individual type sets were allowed to be empty as long as not all sets were empty. llvm-svn: 315858
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-153-3/+3
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFCDaniel Sanders2017-10-151-10/+33
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 llvm-svn: 315843
* [tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders2017-10-153-11/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-143-19/+18
| | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters. llvm-svn: 315826
* [globalisel][tablegen] Simplify named operand/operator lookups and fix a ↵Daniel Sanders2017-10-141-69/+128
| | | | | | | | | | | | | | | | | | | | | | wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
* [globalisel][tablegen] Fix a use-after free bug that manifests on non-macOS ↵Daniel Sanders2017-10-131-1/+1
| | | | | | machines. llvm-svn: 315765
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-133-19/+95
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 ↵Daniel Sanders2017-10-133-28/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use them. Summary: The purpose of this patch is to expose more information about ImmLeaf-like PatLeaf's so that GlobalISel can learn to import them. Previously, ImmLeaf could only be used to test int64_t's produced by sign-extending an APInt. Other tests on immediates had to use the generic PatLeaf and extract the constant using C++. With this patch, tablegen will know how to generate predicates for APInt, and APFloat. This will allow it to 'do the right thing' for both SelectionDAG and GlobalISel which require different methods of extracting the immediate from the IR. This is NFC for SelectionDAG since the new code is equivalent to the previous code. It's also NFC for FastISel because FastIselShouldIgnore is 1 for the ImmLeaf subclasses. Enabling FastIselShouldIgnore == 0 for these new subclasses will require a significant re-factor of FastISel. For GlobalISel, it's currently NFC because the relevant code to import the affected rules is not yet present. This will be added in a later patch. Depends on D36086 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: bjope, aemerson, rengolin, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36534 llvm-svn: 315747
* Revert r315148 [TableGen] Avoid unnecessary std::string creationsDaniel Sanders2017-10-132-13/+13
| | | | | | | | I'm about to commit a patch that makes them necessary for getPredCode() and it would be strange for getPredCode() and getImmCode() to require different usage. llvm-svn: 315733
* [TableGen] : Simplify RegisterInfoEmitterJaved Absar2017-10-131-6/+4
| | | | llvm-svn: 315700
* [TableGen] Allow intrinsics to have up to 8 return values.Artem Belevich2017-10-121-1/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D38633 llvm-svn: 315598
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-123-3/+3
| | | | | | | | | | | | | | | Summary: Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP. Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods. Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so it'll be picked up by public headers. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 315590
* [AsmParser] Suppress compile warning for targets with no register diagsOliver Stannard2017-10-121-11/+17
| | | | | | | This fixes the "switch statement contains 'default' but no 'case' labels" warnings in table-generated code introduced in r315295. llvm-svn: 315571
* Revert "[ADT] Make Twine's copy constructor private."Zachary Turner2017-10-111-2/+2
| | | | | | | | | | This reverts commit 4e4ee1c507e2707bb3c208e1e1b6551c3015cbf5. This is failing due to some code that isn't built on MSVC so I didn't catch. Not immediately obvious how to fix this at first glance, so I'm reverting for now. llvm-svn: 315536
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