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* X86FoldTableEntry - avoid unnecessary std::string creation. NFCI.Simon Pilgrim2018-04-111-3/+3
| | | | llvm-svn: 329860
* Don't repeatedly evaluate size() in the for loop. NFCI.Simon Pilgrim2018-04-111-1/+1
| | | | llvm-svn: 329853
* [MC][TableGen] Fix r329675.Clement Courbet2018-04-101-4/+6
| | | | | | Caught by bots with -Wmissing-braces. llvm-svn: 329676
* [MC][TableGen] Add optional libpfm counter names for ProcResUnits.Clement Courbet2018-04-103-4/+90
| | | | | | | | | | | | | | | | Summary: Subtargets can define the libpfm counter names that can be used to measure cycles and uops issued on ProcResUnits. This allows making llvm-exegesis available on more targets. Fixes PR36984. Reviewers: gchatelet, RKSimon, andreadb, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45360 llvm-svn: 329675
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-064-0/+814
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
* [TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-0611-58/+59
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
* [X86] Disassembler support for having an ADSIZE prefix affect instructions ↵Craig Topper2018-04-052-2/+23
| | | | | | | | with 0xf2 and 0xf3 prefixes. Needed to support umonitor from D45253. llvm-svn: 329327
* Fix the buildbots after r329304.Andrea Di Biagio2018-04-051-1/+1
| | | | llvm-svn: 329306
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-053-3/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [MC] Fix spaces between values printed by EmitRegisterFileInfo.Andrea Di Biagio2018-04-051-2/+2
| | | | llvm-svn: 329284
* [SchedModel] Complete models shouldn't match against itineraries when they ↵Simon Pilgrim2018-04-051-1/+2
| | | | | | | | | | | | don't use them (PR35639) For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp This patch causes problems for a number of models that had been incorrectly flagged as complete. Differential Revision: https://reviews.llvm.org/D43235 llvm-svn: 329280
* [Tablegen] Slightly refactor method SubtargetEmitter::EmitExtraProcessorInfo.Andrea Di Biagio2018-04-041-10/+41
| | | | | | | This patch moves most of the logic from EmitExtraProcessorInfo to a couple of helper functions. No functional change intended. llvm-svn: 329173
* [MC][Tablegen] Allow the definition of processor register files in the ↵Andrea Di Biagio2018-04-033-2/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scheduling model for llvm-mca This patch allows the description of register files in processor scheduling models. This addresses PR36662. A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td. Targets can optionally describe register files for their processors using that class. In particular, class RegisterFile allows to specify: - The total number of physical registers. - Which target registers are accessible through the register file. - The cost of allocating a register at register renaming stage. Example (from this patch - see file X86/X86ScheduleBtVer2.td) def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]> Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar (btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM register definitions only cost 1 physical register. The syntax allows to specify an empty set of register classes. An empty set of register classes means: this register file models all the registers specified by the Target. For each register class, users can specify an optional register cost. By default, register costs default to 1. A value of 0 for the number of physical registers means: "this register file has an unbounded number of physical registers". This patch is structured in two parts. * Part 1 - MC/Tablegen * A first part adds the tablegen definition of RegisterFile, and teaches the SubtargetEmitter how to emit information related to register files. Information about register files is accessible through an instance of MCExtraProcessorInfo. The idea behind this design is to logically partition the processor description which is only used by external tools (like llvm-mca) from the processor information used by the llvm machine schedulers. I think that this design would make easier for targets to get rid of the extra processor information if they don't want it. * Part 2 - llvm-mca related * The second part of this patch is related to changes to llvm-mca. The main differences are: 1) class RegisterFile now needs to take into account the "cost of a register" when allocating physical registers at register renaming stage. 2) Point 1. triggered a minor refactoring which lef to the removal of the "maximum 32 register files" restriction. 3) The BackendStatistics view has been updated so that we can print out extra details related to each register file implemented by the processor. The effect of point 3. is also visible in tests register-files-[1..5].s. Differential Revision: https://reviews.llvm.org/D44980 llvm-svn: 329067
* [X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCICraig Topper2018-04-031-1/+1
| | | | | | TSFlag doesn't need to disambiguate NoPrfx from PS. So shift the encodings so PS is NoPrfx|0x4. llvm-svn: 329049
* [X86][TableGen] Add a missing error check to make sure EVEX instructions use ↵Craig Topper2018-04-031-1/+5
| | | | | | one PS/PD/XS/XD prefixes. llvm-svn: 329048
* [TableGen] Use llvm::cast instead of static_cast so that the cast will be ↵Craig Topper2018-04-031-1/+1
| | | | | | checked. NFC llvm-svn: 329045
* TableGen: Support Intrinsic values in SearchableTableNicolai Haehnle2018-04-011-4/+37
| | | | | | | | | | | | | | | | | | | | | Summary: We will use this in the AMDGPU backend in a subsequent patch in the stack to lookup target-specific per-intrinsic information. The generic CodeGenIntrinsic machinery is used to ensure that, even though we don't calculate actual enum values here, we do get the intrinsics in the right order for the binary search index. Change-Id: If61cd5587963a4c5a1cc53df1e59c5e4dec1f9dc Reviewers: arsenm, rampitec, b-sumner Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D44935 llvm-svn: 328937
* TableGen: More helpful error messagesNicolai Haehnle2018-04-011-2/+6
| | | | | | | | | | | | | Summary: Change-Id: I3c23f6f6597912423762780cd8c5315870412bbe Reviewers: arsenm, rampitec, b-sumner Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44936 Change-Id: Ie62614a3e2d7774f46e4034478b28f57100a2c92 llvm-svn: 328936
* Fix a bunch of typoes. NFCFangrui Song2018-03-302-2/+2
| | | | llvm-svn: 328907
* Add missing dependency (headers are included from MC, so a link dependency ↵David Blaikie2018-03-291-1/+1
| | | | | | could exist easily enough) llvm-svn: 328743
* [SchedModel] Remove instregex entries that don't match any instructionsSimon Pilgrim2018-03-251-2/+11
| | | | | | | | | | This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean. All the cases I encountered have now been fixed in trunk and this will ensure they don't get reintroduced. Differential Revision: https://reviews.llvm.org/D44687 llvm-svn: 328459
* [SchedModel] Remove an unneeded temporary vector.Craig Topper2018-03-241-3/+2
| | | | llvm-svn: 328442
* [SchedModel] Use std::move in a couple places to reduce copyingCraig Topper2018-03-241-2/+3
| | | | llvm-svn: 328441
* [SchedModel] Use std::move to replace a vector instead of vector::swapCraig Topper2018-03-241-1/+1
| | | | | | We don't really care about the old vector value so we don't care to swap it. llvm-svn: 328440
* [SchedModel] Remove std::vectors that were created with 1 element and then ↵Craig Topper2018-03-241-8/+5
| | | | | | | | passed to an ArrayRef parameter. ArrayRef can capture a single element. We don't need a vector for that. llvm-svn: 328438
* [SchedModel] Record::getName() returns StringRef - avoid std::string ↵Simon Pilgrim2018-03-241-2/+2
| | | | | | creation. NFCI. llvm-svn: 328437
* [SchedModel] Avoid std::string creation for instregex patterns that don't ↵Simon Pilgrim2018-03-241-2/+3
| | | | | | contain regex metas. NFCI. llvm-svn: 328436
* [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an ↵Craig Topper2018-03-243-17/+13
| | | | | | | | attribute. This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables. llvm-svn: 328416
* [X86] Use unique_ptr to simplify memory management. NFCCraig Topper2018-03-244-20/+14
| | | | llvm-svn: 328413
* [X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF ↵Craig Topper2018-03-241-24/+5
| | | | | | format encodings. NFC llvm-svn: 328412
* [X86] Remove an unnecessary switch around two other switches. NFCCraig Topper2018-03-241-69/+54
| | | | | | The outer switch only had one valid block so didn't provide any value. llvm-svn: 328411
* [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFCCraig Topper2018-03-242-12/+11
| | | | | | The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map. llvm-svn: 328410
* Fix layering of CodeGen/TargetOpcodes.def by moving it to SupportDavid Blaikie2018-03-231-1/+1
| | | | | | | It's also used by utils/TableGen so needs to reside somewhere common to TableGen and CodeGen. llvm-svn: 328396
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-237-10/+10
| | | | | | | | | This is used by llvm tblgen as well as by LLVM Targets, so the only common place is Support for now. (maybe we need another target for these sorts of things - but for now I'm at least making them correct & we can make them better if/when people have strong feelings) llvm-svn: 328395
* Fix layering by moving X86DisassemblerDecoderCommon to SupportDavid Blaikie2018-03-232-3/+3
| | | | | | | | | This is used from llvm tblgen and the X86Disassembler - the only common library (apart from TableGen, which probably doesn't make sense to have as a dependency from a release tool (rather than a use-while-building-llvm tool) of LLVM) llvm-svn: 328393
* [TableGen] Don't capture returned std::vectors by const reference.Craig Topper2018-03-231-12/+8
| | | | | | The full vector is being returned not a reference. So the reference was just a to a temporary. llvm-svn: 328275
* [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and ↵Craig Topper2018-03-221-4/+4
| | | | | | | | | | VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD This makes the Y position consistent with other instructions. This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary. llvm-svn: 328254
* [TableGen] Use empty emplace_back to add defaulted constructed objects to ↵Craig Topper2018-03-221-10/+8
| | | | | | vectors to avoid using resize(size()+1). NFC llvm-svn: 328184
* [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via ↵Craig Topper2018-03-222-17/+13
| | | | | | emplace_back to create new SchedClasses instead of using resize(size+1) llvm-svn: 328183
* [TableGen] Hoist the code for copying InstRWs from an old scheduling class ↵Craig Topper2018-03-211-12/+12
| | | | | | | | | | to a new one out of the loop that assigns instructions to the new class. NFCI We already know all the of instructions we're processing in the instruction loop belong to no class or all to the same class. So we only have to worry about remapping one class. So hoist it all out and remove the SmallPtrSet that tracked which class we'd already remapped. I had to introduce new instruction loop inside this code to print an error message, but that only occurs on the error path. llvm-svn: 328142
* [TableGen] Remove unnecessary map lookup and shadowing of a variable. NFCICraig Topper2018-03-211-1/+0
| | | | | | We already have an OldSCIdx variable in the outer loop here. And we already did the map lookup in the loop that populated ClassInstrs. And the outer OldSCIdx got it from ClassInstrs. llvm-svn: 328139
* [TableGen] Use range-based for loops. NFCCraig Topper2018-03-211-12/+11
| | | | llvm-svn: 328138
* [TableGen] Use count_if instead of a manual loop. NFCCraig Topper2018-03-211-5/+4
| | | | llvm-svn: 328137
* [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper directly. NFCI.Simon Pilgrim2018-03-211-1/+1
| | | | llvm-svn: 328128
* [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. ↵Simon Pilgrim2018-03-212-6/+4
| | | | | | NFCI. llvm-svn: 328126
* [TableGen] Remove a defaulted function argument that is never called with ↵Craig Topper2018-03-212-5/+3
| | | | | | another value. NFC llvm-svn: 328075
* [TableGen] Move a function from llvm namespace and make it a static ↵Craig Topper2018-03-212-9/+2
| | | | | | | | function. NFC It's only called from one place and is defined just above that use. llvm-svn: 328074
* [TableGen] Use SmallMapVector to simplify some code that was trying to keep ↵Craig Topper2018-03-211-14/+6
| | | | | | | | | | | | | | | | | | | | | a vector unique Summary: This code previously had a SmallVector of std::pairs containing an unsigned and another SmallVector. The outer vector was using the unsigned effectively as a key to decide which SmallVector to add into. So each time something new needed to be added the out vector needed to be scanned. If it wasn't found a new entry needed to be added to be added. This sounds very much like a map, but the next loop iterates over the outer vector to get a deterministic order. We can simplify this code greatly if use SmallMapVector instead. This uses more stack space since we now have a vector and a map, but the searching and creating new entries all happens behind the scenes. It should also make the search more efficient though usually there are only a few entries so that doesn't matter much. We could probably get determinism by just using std::map which would iterate over the unsigned key, but that would generate different output from what we get with the current implementation. Reviewers: RKSimon, dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44711 llvm-svn: 328070
* [SchedModel] Simplify InstRegexOp::apply. NFCI.Simon Pilgrim2018-03-201-24/+27
| | | | | | As discussed on D44687, there was no need for 2 separate for loops for collecting the Regex and then matching against instructions. llvm-svn: 328052
* [TableGen] Use range based for loop. NFCCraig Topper2018-03-201-5/+2
| | | | llvm-svn: 328034
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