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* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-271-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [tblgen] Compare const char * with strcmp instead of creating StringRef.Benjamin Kramer2016-07-261-2/+2
| | | | | | | Avoids a call to strlen on both strings which always reads the entire string. strcmp can use early exit. llvm-svn: 276737
* GlobalISel: Remove explicit enumerator values from .def file.Tim Northover2016-07-201-1/+1
| | | | | | | | | | They were all auto-incremented from 0 anyway, and I'm getting really annoying conflicts and runtime failures when different people add more for GlobalISel (and even when I'm refactoring my own patches). NFC. llvm-svn: 276204
* TableGen: Allow custom register operand decoder methodMatt Arsenault2016-07-181-25/+33
| | | | | | | | | | | | | | | | | | This is for a situation where the encoding for a register may be different depending on the specific operand. For some instructions, we want to apply additional restrictions beyond the encoding's constraints. In AMDGPU some operands are VSrc_32, using the VS_32 pseudo register class which accept VGPRs, SGPRs, or immediates in the encoding. Some specific instructions with the same encoding operand do not want to allow immediates or SGPRs, but the encoding format is different in this case than a regular VGPR_32 operand. This allows specifying the encoding should be treated the same without introducing yet another dummy register class. llvm-svn: 275929
* IR: Sort generic intrinsics before target specific onesJustin Bogner2016-07-155-39/+78
| | | | | | | | | | | | This splits out the intrinsic table such that generic intrinsics come first and target specific intrinsics are grouped by target. From here we can find out which target an intrinsic is for or differentiate between generic and target intrinsics. The motivation here is to make it easier to move target specific intrinsic handling out of generic code. llvm-svn: 275575
* TableGen: Fix a confusing use of both i and I as variables. NFCJustin Bogner2016-07-141-5/+5
| | | | llvm-svn: 275450
* XRay: Add entry and exit sledsDean Michael Berris2016-07-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: In this patch we implement the following parts of XRay: - Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches. - Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts). - X86-specific nop sleds as described in the white paper. - A machine function pass that adds the different instrumentation marker instructions at a very late stage. - A way of identifying which return opcode is considered "normal" for each architecture. There are some caveats here: 1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet. 2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library. Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D19904 llvm-svn: 275367
* Add a 'Returned' intrinsic property corresponding to the 'returned' argument ↵Hal Finkel2016-07-113-1/+10
| | | | | | | | | | attribute This will be used by the upcoming llvm.noalias intrinsic. Differential Revision: http://reviews.llvm.org/D22201 llvm-svn: 275034
* TableGen: Update style in CodeGenIntrinsics. NFCJustin Bogner2016-07-081-103/+96
| | | | | | | | Ran clang-format to remove the namespace indentation, and stopped repeating names in doc comments since I was updating every line anyway. llvm-svn: 274919
* TableGen: avoid string copy.Tim Northover2016-07-051-1/+1
| | | | llvm-svn: 274584
* AArch64: TableGenerate system instruction operands.Tim Northover2016-07-054-1/+329
| | | | | | | | | | | | | | | | | | | | The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
* TableGen: promote "code" type from syntactic sugar.Tim Northover2016-07-051-1/+1
| | | | | | | It's being immediately converted to a "string", but being able to tell what type the field was originally can be useful in backends. llvm-svn: 274575
* [TableGen] Remove dead code. NFCI.Davide Italiano2016-07-041-28/+0
| | | | llvm-svn: 274515
* Add writeonly IR attributeNicolai Haehnle2016-07-043-1/+20
| | | | | | | | | | | | | | | | | Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
* Revert "Revert "[misched] Extend scheduler to handle unsupported features""Simon Dardis2016-06-242-1/+37
| | | | | | | | This reverts commit r273565. This was an over-eager revert. llvm-svn: 273658
* [TableGen] Use StringRef::compare instead of != and <. NFC.Ahmed Bougacha2016-06-231-2/+2
| | | | | | | | | The previous code would always do 1 or 2 prefix compares; explicitly only do one. This speeds up debug -gen-asm-matcher by ~10% (e.g. X86: 40s -> 35s). llvm-svn: 273583
* Revert "[misched] Extend scheduler to handle unsupported features"Simon Dardis2016-06-232-37/+1
| | | | | | | | This reverts commit r273551. Patch contained a wrong check for isUnsupported. llvm-svn: 273565
* [misched] Extend scheduler to handle unsupported featuresSimon Dardis2016-06-232-1/+37
| | | | | | | | | | | | | | | | | | | | | | | Currently isComplete = 1 requires that every instruction must be described, declared unsupported or marked as having no scheduling information for a processor. For some backends such as MIPS, this requirement entails long regex lists of instructions that are unsupported. This patch teaches Tablegen to skip over instructions that are associated with unsupported feature when checking if the scheduling model is complete. Patch by: Daniel Sanders Contributions by: Simon Dardis Reviewers: MatzeB Differential Reviewer: http://reviews.llvm.org/D20522 llvm-svn: 273551
* TableGen/CodeGenSchedule: Move some getAllDerivedDefinitions() calls out of ↵Matthias Braun2016-06-212-3/+11
| | | | | | | | | inner loops This cuts the runtime of the two slowest tblgen invocations in aarch64 in half for me... llvm-svn: 273235
* test commit: remove trailing whitespaceThomas Jablin2016-06-201-1/+1
| | | | llvm-svn: 273197
* Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2016-06-122-2/+2
| | | | | | No functionality change intended. llvm-svn: 272516
* Search for llvm-symbolizer binary in the same directory as argv[0], beforeRichard Smith2016-06-091-1/+1
| | | | | | | looking for it along $PATH. This allows installs of LLVM tools outside of $PATH to find the symbolizer and produce pretty backtraces if they crash. llvm-svn: 272232
* Apply most suggestions of clang-tidy's performance-unnecessary-value-paramBenjamin Kramer2016-06-084-16/+13
| | | | | | | Avoids unnecessary copies. All changes audited & pass tests with asan. No functional change intended. llvm-svn: 272190
* AsmWriterEmitter.cpp assumes that all operands of a printed aliasSjoerd Meijer2016-06-031-3/+4
| | | | | | | | | | | will appear after a blank. This assumption does not hold in the ARM target. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20234 llvm-svn: 271666
* Currently AsmWriterEmiter.cpp (used by tblgen -gen-asm-writer) does notSjoerd Meijer2016-06-031-2/+34
| | | | | | | | | | | | | consider the Predicates attached to InstAlias when generating printAliasInstr. This forces users of printAliasInstr to check those predicates beforehand. This commit adds them in the condition set of the IAPrinter object. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20233 llvm-svn: 271665
* Apply clang-tidy's misc-move-constructor-init throughout LLVM.Benjamin Kramer2016-05-274-16/+18
| | | | | | No functionality change intended, maybe a tiny performance improvement. llvm-svn: 270997
* Avoid some copies by using const references.Benjamin Kramer2016-05-271-1/+1
| | | | | | | clang-tidy's performance-unnecessary-copy-initialization with some manual fixes. No functional changes intended. llvm-svn: 270988
* TableGen: Use StringRef instead of std::stringMatt Arsenault2016-05-252-4/+4
| | | | llvm-svn: 270741
* Fix Clang-tidy modernize-use-bool-literals in generated Target code; other ↵Eugene Zelenko2016-05-172-51/+80
| | | | | | | | | | | | minor fixes; other minor fixes. Make generated code more readable. Fix some Include What You Use warnings. Differential revision: http://reviews.llvm.org/D20317 llvm-svn: 269783
* SDAG: Make SelectCodeCommon return voidJustin Bogner2016-05-101-2/+3
| | | | | | | | | | | This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
* [TableGen] AsmMatcher: support for default values for optional operandsSam Kolton2016-05-061-31/+117
| | | | | | | | | | | | | | Summary: This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst. Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented. Reviewers: tstellarAMD, ab, craig.topper Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits Differential Revision: http://reviews.llvm.org/D18242 llvm-svn: 268726
* [TableGen] Fix a memory leak when creating SwitchOpcodeMatchers.Craig Topper2016-05-061-1/+2
| | | | llvm-svn: 268712
* [TableGen] Remove isSafeToReorderWithPatternPredicate from DAGISelMatchers ↵Craig Topper2016-05-061-49/+0
| | | | | | as its not used anymore. llvm-svn: 268711
* [TableGen] Remove getHash support from DAGISelMatcher. It hasn't been used ↵Craig Topper2016-05-062-95/+0
| | | | | | for some time. llvm-svn: 268706
* [TableGen] Remove SinkPatternPredicates from the DAG isel matcher optimizer.Craig Topper2016-05-061-54/+0
| | | | | | Pattern predicates already appear to be emitted as far down as they can be. The optimization was making no changes on any in-tree target. llvm-svn: 268705
* SDAG: Remove OPC_MarkGlueResults and associated logic. NFCJustin Bogner2016-05-055-76/+0
| | | | | | | | | This opcode never happens in practice, and yet the logic we have in place to handle it would be undefined behaviour if we ever executed it. Remove it rather than trying to refactor code that's never reached. llvm-svn: 268692
* [TableGen] Make sure to recursively factor any ScopeMatchers created while ↵Craig Topper2016-05-051-1/+3
| | | | | | forming a SwitchType node. Remove a couple hundred bytes from the X86 matcher table. llvm-svn: 268611
* [TableGen] Remove stale comment.Craig Topper2016-05-051-2/+1
| | | | llvm-svn: 268610
* [CodeGen] Add some space optimized forms of EmitNode and MorphNodeTo that ↵Craig Topper2016-05-031-5/+12
| | | | | | | | implicitly indicate the number of result VTs. This shaves about 16K off the X86 matching table taking it down to about 470K. Overall this reduces the llc binary size with all in-tree targets by about 40K. llvm-svn: 268365
* [CodeGen] Add OPC_MoveChild0-OPC_MoveChild7 opcodes to isel matching tables ↵Craig Topper2016-05-021-3/+10
| | | | | | to optimize table size. Shaves about 12K off the X86 matcher table. llvm-svn: 268209
* TableGen: Produce CoveredBySubRegs summary for register classesMatthias Braun2016-04-283-3/+9
| | | | | | This will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267850
* TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()Matthias Braun2016-04-281-12/+29
| | | | | | | | | This function performs the reverse computation of composeSubRegIndexLaneMask(). It will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267849
* TableGen: Support lanemasks for classes without subregistersMatthias Braun2016-04-281-38/+50
| | | | | | | | | | | | | Previously using lanemasks on registers without any subregisters was not well defined. This commit extends TargetRegisterInfo/tablegen to: - Report a lanemask of 1 for regclasses without subregisters - Do the right thing when mapping a 0/1 lanemask from a class without subregisters into a class with subregisters in TargetRegisterInfo::composeSubRegIndexLaneMasks(). This will be used in the upcoming "DetectDeadLanes" patch. llvm-svn: 267848
* Split IntrReadArgMem into IntrReadMem and IntrArgMemOnlyNicolai Haehnle2016-04-212-9/+5
| | | | | | | | | | | | | | | | | | Summary: IntrReadWriteArgMem simply becomes IntrArgMemOnly. So there are fewer intrinsic properties that express their orthogonality better, and correspond more closely to the corresponding IR attributes. Suggested by: Philip Reames Reviewers: joker.eph, reames, tstellarAMD Subscribers: jholewinski, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19291 llvm-svn: 267021
* Add LLVMGetAttrKindID in the C API in order to facilitate migration away ↵Amaury Sechet2016-04-201-0/+23
| | | | | | | | | | | | | | | | | from LLVMAttribute Summary: LLVMAttribute has outlived its utility and is becoming a problem for C API users that what to use all the LLVM attributes. In order to help moving away from LLVMAttribute in a smooth manner, this diff introduce LLVMGetAttrKindIDInContext, which can be used instead of the enum values. See D18749 for reference. Reviewers: Wallbraker, whitequark, joker.eph, echristo, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19081 llvm-svn: 266842
* Add IntrWrite[Arg]Mem intrinsic propertyNicolai Haehnle2016-04-194-9/+40
| | | | | | | | | | | | | | | | | | | | | | Summary: This property is used to mark an intrinsic that only writes to memory, but neither reads from memory nor has other side effects. An example where this is useful is the llvm.amdgcn.buffer.store.format.* intrinsic, which corresponds to a store instruction that goes through a special buffer descriptor rather than through a plain pointer. With this property, the intrinsic should still be handled as having side effects at the LLVM IR level, but machine scheduling can make smarter decisions. Reviewers: tstellarAMD, arsenm, joker.eph, reames Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18291 llvm-svn: 266826
* [TableGen] Make an error message slightly more informativeNicolai Haehnle2016-04-191-2/+9
| | | | | | | | | | Reviewers: ab, spop, stoklund Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19192 llvm-svn: 266823
* [NFC] Header cleanupMehdi Amini2016-04-1810-14/+4
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* Declare MVT::SimpleValueType as an int8_t sized enum. This removes 400 bytes ↵Craig Topper2016-04-171-3/+5
| | | | | | | | | | from TargetLoweringBase and probably other places. This required changing several places to print VT enums as strings instead of raw ints since the proper method to use to print became ambiguous. This is probably an improvement anyway. This also appears to save ~8K from an x86 self host build of llc. llvm-svn: 266562
* Update and fix LLVM_ENABLE_MODULES:Richard Smith2016-04-161-4/+0
| | | | | | | | | | | | | | | | 1) We need to add this flag prior to adding any other, in case the user has specified a -fmodule-cache-path= flag in their custom CXXFLAGS. Such a flag causes -Werror builds to fail, and thus all config checks fail, until we add the corresponding -fmodules flag. The modules selfhost bot does this, for instance. 2) Delete module maps that were putting .cpp files into modules. 3) Enable -fmodules-local-submodule-visibility, to get proper module visibility rules applied across submodules of the same module. Disable -fmodules for C builds, since that flag is not available there. llvm-svn: 266502
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