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* [TableGen] Use StringRef to capture getValueAsString in a couple more ↵Craig Topper2017-06-011-2/+2
| | | | | | places. NFC llvm-svn: 304386
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-3113-75/+78
| | | | | | instead of a std::string. llvm-svn: 304347
* [TableGen] Make Record::getValueAsString and getValueAsListOfStrings return ↵Craig Topper2017-05-316-24/+32
| | | | | | | | | | | | StringRefs instead of std::string Internally both these methods just return the result of getValue on either a StringInit or a CodeInit object. In both cases this returns a StringRef pointing to a string allocated in the BumpPtrAllocator so its not going anywhere. So we can just pass that StringRef along. This is a fairly naive patch that targets just the build failures caused by this change. There's additional work that can be done to avoid creating std::string at call sites that still think getValueAsString returns a std::string. I'll try to clean those up in future patches. Differential Revision: https://reviews.llvm.org/D33710 llvm-svn: 304325
* [TableGen] Introduce DagInit::getArgs that returns an ArrayRef. Use it to ↵Craig Topper2017-05-291-1/+1
| | | | | | fix 80 column violations in arg_begin/arg_end. Remove DagInit::args and use getArgs instead. NFC llvm-svn: 304177
* [X86] Don't fold away the memory operand of an xchg.Benjamin Kramer2017-05-291-1/+8
| | | | | | | | | | xchg with a mem operand has different locking semantics. If we unfold it into a xchg r,r we will loose the implicit lock. Likewise we never want to fold a register xchg into a memory one as it would be a lot slower. This triggers during LLVM selfhost. llvm-svn: 304163
* Don't capture a temporary std::string in a StringRef.Zachary Turner2017-05-291-1/+1
| | | | | | This fixes the breakages in llvm-tblgen. llvm-svn: 304123
* Resubmit "[X86] Adding new LLVM TableGen backend that generates the X86 ↵Zachary Turner2017-05-294-0/+728
| | | | | | | | | | | | | backend memory folding tables." This was reverted due to buildbot breakages and I was not familiar with this code to investigate it. But while trying to get a useful backtrace for the author, it turns out the fix was very obvious. Resubmitting this patch as is, and will submit the fix in a followup so that the fix is not hidden in the larger CL. llvm-svn: 304122
* Revert "[X86] Adding new LLVM TableGen backend that generates the X86 ↵Zachary Turner2017-05-294-728/+0
| | | | | | | | | | | | | backend memory folding tables." This reverts commit 28cb1003507f287726f43c771024a1dc102c45fe as well as all subsequent followups. llvm-tblgen currently segfaults with this change, and it seems it has been broken on the bots all day with no fixes in preparation. See, for example: http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/ llvm-svn: 304121
* [TableGen][X86] Fix formatting I accidentally messed up in r304099. NFCCraig Topper2017-05-281-1/+1
| | | | llvm-svn: 304115
* [TableGen][X86] Use CHAR_BIT with sizeof instead of hardcoded 8. NFCCraig Topper2017-05-281-1/+2
| | | | llvm-svn: 304100
* [TableGen][X86] Mark a couple global tables as const. NFCCraig Topper2017-05-281-2/+2
| | | | llvm-svn: 304099
* [TableGen][X86] Improve formatting of the fold table output by indenting the ↵Craig Topper2017-05-281-2/+2
| | | | | | body of the table and adding blank lines between tables. NFC llvm-svn: 304098
* [TableGen][X86] Add an llvm_unreachable to a switch so we get an error if we ↵Craig Topper2017-05-281-0/+1
| | | | | | need expansion in the future. llvm-svn: 304097
* [TableGen][X86] Remove unnecessary std::string creations. NFCCraig Topper2017-05-281-4/+4
| | | | llvm-svn: 304096
* [TableGen][X86] Replace a global std::vector with a regular array. ↵Craig Topper2017-05-281-2/+2
| | | | | | llvm::find works on arrays, just need to use std::end to check the result. llvm-svn: 304095
* [TableGen][X86] getValueAsString returns a std::string not a StringRef. ↵Craig Topper2017-05-281-1/+1
| | | | | | Capture it that way to avoid a StringRef to a temporary. llvm-svn: 304093
* [X86] Adding new LLVM TableGen backend that generates the X86 backend memory ↵Ayman Musa2017-05-284-0/+726
| | | | | | | | | | | folding tables. X86 backend holds huge tables in order to map between the register and memory forms of each instruction. This TableGen Backend automatically generated all these tables with the appropriate flags for each entry. Differential Revision: https://reviews.llvm.org/D32684 llvm-svn: 304088
* Fixed nondeterminism in RuleMatcher::emit.Galina Kistanova2017-05-251-1/+8
| | | | llvm-svn: 303829
* Fix unused variable warnings after r303678Daniel Sanders2017-05-231-2/+2
| | | | | | This should fix lld-x86_64-darwin13 llvm-svn: 303683
* [globalisel][tablegen] Add support for (set $dst, 1) and test X86's ↵Daniel Sanders2017-05-231-18/+65
| | | | | | | | | | | | | | | | | | | | | | | | | OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
* Revert r303259 - [globalisel][tablegen] Import rules containing ↵Daniel Sanders2017-05-221-22/+3
| | | | | | | | | | | intrinsic_wo_chain. It's causing some buildbots to timeout whenever tablegen needs re-compilation, particularly those with -fsanitize=memory but not only them. A compile time regression was expected since it triples the amount of SelectionDAG rules we are able to import but it's currently too high. llvm-svn: 303542
* [MVT] add v1i1 MVTGuy Blank2017-05-181-0/+2
| | | | | | | | Adds the v1i1 MVT as a preparation for another commit (https://reviews.llvm.org/D32273) Differential Revision: https://reviews.llvm.org/D32540 llvm-svn: 303346
* Re-commit: [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-05-181-3/+22
| | | | | | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 The previous commit failed on test-suite/Bitcode/simd_ops/AArch64_halide_runtime.bc because isImmOperandEqual() assumed MO was a register operand and that's not always true. llvm-svn: 303341
* Revert "[globalisel][tablegen] Import rules containing intrinsic_wo_chain."Quentin Colombet2017-05-171-22/+3
| | | | | | | | | This reverts commit r303259. This breaks the GISel bot: http://lab.llvm.org:8080/green/job/Compiler_Verifiers_GlobalISEL/5163/consoleFull#-134276167849ba4694-19c4-4d7e-bec5-911270d8a58c llvm-svn: 303313
* [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-05-171-3/+22
| | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 303259
* [globalisel][tablegen] Require that all registers between instructions of a ↵Daniel Sanders2017-05-171-0/+2
| | | | | | | | | | | | | | | | | | | match are virtual. Summary: Without this, it's possible to encounter multiple defs for a register. This is triggered by the current version of D32868 when applied to trunk. Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls Reviewed By: qcolombet Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32869 llvm-svn: 303253
* Fixup r303240: Use llvm::to_string instead of std::to_stringDiana Picus2017-05-171-3/+3
| | | | | | | It turns out some of the buildbots don't have std::to_string around, even in this day and age... llvm-svn: 303243
* [GlobalISel][TableGen] Fix handling of default operandsDiana Picus2017-05-171-48/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
* Added LLVM_DUMP_METHOD attributes for MatchableInfo::dump(). Defined it only ↵Galina Kistanova2017-05-171-1/+3
| | | | | | if dump is enabled. llvm-svn: 303229
* [TableGen] Add EncoderMethod to RegisterOperandSam Kolton2017-05-151-0/+1
| | | | | | | | Reviewers: stoklund, grosbach, vpykhtin Differential Revision: https://reviews.llvm.org/D32493 llvm-svn: 303044
* [X86] Moving X86Local namespace from .cpp to .h file to use it in memory ↵Ayman Musa2017-05-112-124/+123
| | | | | | | | folding TableGen backend. Differential Revision: https://reviews.llvm.org/D32797 llvm-svn: 302791
* Fix comment typos.Geoff Berry2017-05-081-1/+1
| | | | llvm-svn: 302432
* [IR] Abstract away ArgNo+1 attribute indexing as much as possibleReid Kleckner2017-05-031-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Do three things to help with that: - Add AttributeList::FirstArgIndex, which is an enumerator currently set to 1. It allows us to change the indexing scheme with fewer changes. - Add addParamAttr/removeParamAttr. This just shortens addAttribute call sites that would otherwise need to spell out FirstArgIndex. - Remove some attribute-specific getters and setters from Function that take attribute list indices. Most of these were only used from BuildLibCalls, and doesNotAlias was only used to test or set if the return value is malloc-like. I'm happy to split the patch, but I think they are probably easier to review when taken together. This patch should be NFC, but it sets the stage to change the indexing scheme to this, which is more convenient when indexing into an array: 0: func attrs 1: retattrs 2...: arg attrs Reviewers: chandlerc, pete, javed.absar Subscribers: david2050, llvm-commits Differential Revision: https://reviews.llvm.org/D32811 llvm-svn: 302060
* Support arbitrary address space pointers in masked gather/scatter intrinsics.Elad Cohen2017-05-031-5/+11
| | | | | | | | | | | | Fixes PR31789 - When loop-vectorize tries to use these intrinsics for a non-default address space pointer we fail with a "Calling a function with a bad singature!" assertion. This patch solves this by adding the 'vector of pointers' argument as an overloaded type which will determine the address space. Differential revision: https://reviews.llvm.org/D31490 llvm-svn: 302018
* [ARM] GlobalISel: Use TableGen instruction selectorDiana Picus2017-05-021-3/+9
| | | | | | | | | | | Emit and use the TableGen instruction selector for ARM. At the moment, this allows us to remove the hand-written code for selecting G_SDIV and G_UDIV. Future commits will focus on increasing the code coverage for it and removing more dead code from the current instruction selector. llvm-svn: 301905
* [globalisel][tablegen] Silence unused variable warning.Daniel Sanders2017-04-291-1/+0
| | | | llvm-svn: 301755
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-293-47/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 llvm-svn: 301750
* TableGen: Add IntrHasSideEffects property for intrinsicsMatt Arsenault2017-04-284-1/+12
| | | | | | | | | | | | | | | The IntrNoMem, IntrReadMem, IntrWriteMem, and IntrArgMemOnly intrinsic properties differ from their corresponding LLVM IR attributes by specifying that the intrinsic, in addition to its memory properties, has no other side effects. The IntrHasSideEffects flag used in combination with one of the memory flags listed above, makes it possible to define an intrinsic such that its properties at the CodeGen layer match its properties at the IR layer. Patch by Tom Stellard llvm-svn: 301685
* Add speculatable function attributeMatt Arsenault2017-04-283-1/+16
| | | | | | | | This attribute tells the optimizer that the function may be speculated. Patch by Tom Stellard llvm-svn: 301680
* Fixed assert message to correctly refer to MRMSrcReg4VOp3Frm/MRMSrcMeg4VOp3Frm.Simon Pilgrim2017-04-271-2/+2
| | | | llvm-svn: 301544
* [globalisel][tablegen] Fix vector element sizeIgor Breger2017-04-261-1/+1
| | | | | | | | | | | | | | Summary: Fix vector element size. Reviewers: dsanders Reviewed By: dsanders Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32537 llvm-svn: 301421
* [globalisel][tablegen] Add support for RegisterOperand.Daniel Sanders2017-04-221-1/+10
| | | | | | | | | | | | | | | | | | Summary: It functions just like RegisterClass except that the class is obtained from a field. Depends on D31761. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: dberris, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32229 llvm-svn: 301080
* [globalisel][tablegen] Revise API for ComplexPattern operands to improve ↵Daniel Sanders2017-04-221-103/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flexibility. Summary: Some targets need to be able to do more complex rendering than just adding an operand or two to an instruction. For example, it may need to insert an instruction to extract a subreg first, or it may need to perform an operation on the operand. In SelectionDAG, targets would create SDNode's to achieve the desired effect during the complex pattern predicate. This worked because SelectionDAG had a form of garbage collection that would take care of SDNode's that were created but not used due to a later predicate rejecting a match. This doesn't translate well to GlobalISel and the churn was wasteful. The API changes in this patch enable GlobalISel to accomplish the same thing without the waste. The API is now: InstructionSelector::OptionalComplexRendererFn selectArithImmed(MachineOperand &Root) const; where Root is the root of the match. The return value can be omitted to indicate that the predicate failed to match, or a function with the signature ComplexRendererFn can be returned. For example: return OptionalComplexRendererFn( [=](MachineInstrBuilder &MIB) { MIB.addImm(Immed).addImm(ShVal); }); adds two immediate operands to the rendered instruction. Immed and ShVal are captured from the predicate function. As an added bonus, this also reduces the amount of information we need to provide to GIComplexOperandMatcher. Depends on D31418 Reviewers: aditya_nandakumar, t.p.northover, qcolombet, rovka, ab, javed.absar Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31761 llvm-svn: 301079
* [globalisel][tablegen] Fix PR32733 by checking which instruction operands ↵Daniel Sanders2017-04-221-2/+3
| | | | | | | | | | | | | belong to. canMutate() was returning true when the operands were all in the same order as the matched instruction. However, it wasn't checking the operands were actually on that instruction. This worked when we could only match a single instruction but the addition of nested instruction matching led to cases where the operands could be split across multiple instructions. canMutate() now returns false if operands belong to instructions other than the root of the match. llvm-svn: 301077
* [globalisel][tablegen] Import SelectionDAG's rule predicates and support the ↵Daniel Sanders2017-04-216-27/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
* Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule ↵Daniel Sanders2017-04-216-141/+27
| | | | | | | | | predicates and support the equivalent in GIRule. It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I haven't worked out why. Reverting to make it green while I figure it out. llvm-svn: 300978
* [globalisel][tablegen] Try again to fix builds on old MSVC's after r300964Daniel Sanders2017-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This should fix llvm-clang-x86_64-expensive-checks-win I reproduced the error using the following code: namespace llvm { // Moving this out of the llvm namespace fixes the error. template<unsigned NumBits> class PredicateBitsetImpl {}; } namespace { const unsigned MAX_SUBTARGET_PREDICATES = 11; // This works on Clang but is broken on MSVC // using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; // Some versions emit a syntax error here ("error C2061: syntax error: identifier // 'PredicateBitsetImpl'") but others accept it and only emit the C3646 below. // // This works on Clang and MSVC using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; class Foo { private: PredicateBitset A; // error C3646: 'A': unknown override specifier }; } llvm-svn: 300970
* Revert: r300966 - [globalisel][tablegen] Attempt to fix builds on old MSVC's ↵Daniel Sanders2017-04-211-2/+2
| | | | | | | | after r300964 It didn't fix the builder. llvm-svn: 300968
* [globalisel][tablegen] Attempt to fix builds on old MSVC's after r300964Daniel Sanders2017-04-211-2/+2
| | | | | | This should fix llvm-clang-x86_64-expensive-checks-win llvm-svn: 300966
* [globalisel][tablegen] Import SelectionDAG's rule predicates and support the ↵Daniel Sanders2017-04-216-27/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300964
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