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* Tidyup P->getComplexPatternInfo call by moving it inside if( != NULL) test. ↵Simon Pilgrim2017-09-261-3/+1
| | | | | | NFCI. llvm-svn: 314202
* [TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek2017-09-225-33/+56
| | | | | | | | | | Also add operator<< for use with raw_ostream to InfoByHwMode and its derived classes. Recommitting r313989 with the fix for unresolved references: explicitly define the operator<< in namespace llvm. llvm-svn: 314004
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-09-222-13/+13
| | | | llvm-svn: 313996
* Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"Krzysztof Parzyszek2017-09-225-53/+33
| | | | | | This reverts commit r313989: it breaks Windows bots. llvm-svn: 313990
* [TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek2017-09-225-33/+53
| | | | | | | Also add operator<< for use with raw_ostream to InfoByHwMode and its derived classes. llvm-svn: 313989
* [TableGen] Return StringRef from ValueTypeByHwMode::getMVTNameSimon Pilgrim2017-09-222-6/+5
| | | | | | | | | | Avoid unnecessary std::string creations during TypeSetByHwMode::writeToStream. Found during investigations into PR28222 Differential Revision: https://reviews.llvm.org/D38174 llvm-svn: 313983
* [TableGen] Tidy up CodeGenRegistersJaved Absar2017-09-211-28/+23
| | | | | | | | | Replacing range loops. Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38091 llvm-svn: 313874
* [TableGen] Use CHAR_BIT instead of hardcoded 8 with sizeof. NFCCraig Topper2017-09-211-1/+1
| | | | llvm-svn: 313860
* [TableGen] Include StringMap.h instead of StringSet.h since that's the data ↵Craig Topper2017-09-211-1/+1
| | | | | | structure we use. llvm-svn: 313859
* [TableGen] Some optimizations to TableGen.Zachary Turner2017-09-202-44/+52
| | | | | | | | | This changes some STL data types to corresponding LLVM data types that have better performance characteristics. Differential Revision: https://reviews.llvm.org/D37957 llvm-svn: 313783
* [TableGen] Generate formatted DAGISelEmitter without relying on ↵Craig Topper2017-09-191-91/+93
| | | | | | | | | | | | | | formatted_raw_ostream. The generated DAG isel file currently makes use of formatted_raw_ostream primarily for generating a hierarchical representation while also skipping over the initial comment that contains the current index. It was reported in D37957 that this formatting might be slow due to the need to keep track of column numbers by monitoring all the written data for new lines. This patch attempts to rewrite the emitter to make use of simpler formatting mechanisms to generate a fairly similar output. The main difference is that the number in the index comment is now right justified and padded with spaces inside the comment. Previously we appended the spaces after the comment. Differential Revision: https://reviews.llvm.org/D37966 llvm-svn: 313674
* Recommit r313647 now that GCC seems to accept the offeringKrzysztof Parzyszek2017-09-193-45/+230
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some member types to MachineValueTypeSet::const_iterator so that iterator_traits can work with it. Improve TableGen performance of -gen-dag-isel (motivated by X86 backend) The introduction of parameterized register classes in r313271 caused the matcher generation code in TableGen to run much slower, particularly so in the unoptimized (debug) build. This patch recovers some of the lost performance. Summary of changes: - Cache the set of legal types in TypeInfer::getLegalTypes. The contents of this set do not change. - Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally this would not be necessary, but in the debug build TableGen is not optimized, so this helps a little bit. - Add an early exit from TypeSetByHwMode::operator== for the case when one or both arguments are "simple", i.e. only have one mode. This saves some time in GenerateVariants. - Finally, replace the underlying storage type in TypeSetByHwMode::SetType with MachineValueTypeSet based on std::array instead of std::set. This significantly reduces the number of memory allocation calls. I've done a number of experiments with the underlying type of InfoByHwMode. The type is a map, and for targets that do not use the parameterization, this map has only one entry. The best (unoptimized) performance, somewhat surprisingly came from std::map, followed closely by std::unordered_map. DenseMap was the slowest by a large margin. Various hand-crafted solutions (emulating enough of the map interface not to make sweeping changes to the users) did not yield any observable improvements. llvm-svn: 313660
* Revert "Improve TableGen performance of -gen-dag-isel (motivated by X86 ↵Krzysztof Parzyszek2017-09-193-222/+45
| | | | | | | | backend)" It breaks a lot of bots due to missing "__iterator_category". llvm-svn: 313651
* Move "(void)variable" closer to the assertion that uses it, NFCKrzysztof Parzyszek2017-09-191-1/+1
| | | | llvm-svn: 313649
* Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)Krzysztof Parzyszek2017-09-193-45/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The introduction of parameterized register classes in r313271 caused the matcher generation code in TableGen to run much slower, particularly so in the unoptimized (debug) build. This patch recovers some of the lost performance. Summary of changes: - Cache the set of legal types in TypeInfer::getLegalTypes. The contents of this set do not change. - Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally this would not be necessary, but in the debug build TableGen is not optimized, so this helps a little bit. - Add an early exit from TypeSetByHwMode::operator== for the case when one or both arguments are "simple", i.e. only have one mode. This saves some time in GenerateVariants. - Finally, replace the underlying storage type in TypeSetByHwMode::SetType with MachineValueTypeSet based on std::array instead of std::set. This significantly reduces the number of memory allocation calls. I've done a number of experiments with the underlying type of InfoByHwMode. The type is a map, and for targets that do not use the parameterization, this map has only one entry. The best (unoptimized) performance, somewhat surprisingly came from std::map, followed closely by std::unordered_map. DenseMap was the slowest by a large margin. Various hand-crafted solutions (emulating enough of the map interface not to make sweeping changes to the users) did not yield any observable improvements. llvm-svn: 313647
* [globalisel] Add support for intrinsic_w_chain.Daniel Sanders2017-09-191-3/+5
| | | | | | This maps directly to G_INTRINSIC_W_SIDE_EFFECTS. llvm-svn: 313627
* Remove uses of deprecated std::not1.Benjamin Kramer2017-09-171-3/+3
| | | | | | | Lambdas are slightly more verbose, but also more readable. No functionality change intended. llvm-svn: 313482
* Fix selecting legal types in TypeInfer::getLegalTypesKrzysztof Parzyszek2017-09-151-9/+3
| | | | | | Collect all legal types for all modes. llvm-svn: 313380
* Subtarget support for parameterized register class informationKrzysztof Parzyszek2017-09-141-5/+27
| | | | | | | | Implement "checkFeatures" and emitting HW mode check code. Differential Revision: https://reviews.llvm.org/D31959 llvm-svn: 313295
* Remove usages of deprecated std::unary_function and std::binary_function.Benjamin Kramer2017-09-141-1/+1
| | | | | | | | | | These are removed in C++17. We still have some users of unary_function::argument_type, so just spell that typedef out. No functionality change intended. Note that many of the argument types are actually wrong :) llvm-svn: 313287
* Silence warning about unused variable in release buildKrzysztof Parzyszek2017-09-141-0/+1
| | | | llvm-svn: 313273
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-1418-1045/+2052
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* [tblgen] Remove uses of std::ptr_fun, it's removed in C++17.Benjamin Kramer2017-09-141-8/+5
| | | | | | No functionality change intended. llvm-svn: 313269
* [MiSched|TableGen] : Tidy up and modernise. NFC.Javed Absar2017-09-132-113/+99
| | | | | | | | | Replacing with range-based loop and substituting 'using'. Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D37748 llvm-svn: 313140
* Remove ancient, commented out code from TableGen, NFCKrzysztof Parzyszek2017-09-122-16/+0
| | | | | | These pieces were commented out in r98534 and r129691, i.e. 6+ years ago. llvm-svn: 313038
* Formatting changes, add LLVM_DUMP_METHOD to a dump function, NFCKrzysztof Parzyszek2017-09-122-6/+6
| | | | llvm-svn: 313037
* [TableGen] Ensure that __lsan_is_turned_off isn't removed by DCE in llvm-tblgenFrancis Ricci2017-09-111-1/+1
| | | | | | | | | | | | | | Summary: Since asan is linked dynamically on Darwin, the weak interface symbol is removed by -Wl,-dead_strip. Reviewers: kcc, compnerd, aaron.ballman Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37636 llvm-svn: 312914
* [TableGen] Teach tablegen to allow SDNPCommutable nodes with more than 2 ↵Craig Topper2017-09-041-4/+9
| | | | | | | | | | | | | | | | | | | operands. Summary: Tablegen already supports commutable instrinsics with more than 2 operands. There it just assumes the first two operands are commutable. I plan to use this to improve the generation of FMA patterns in the X86 backend. Reviewers: aymanmus, zvi, RKSimon, spatel, arsenm Reviewed By: arsenm Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D37430 llvm-svn: 312464
* [TableGen] Fix a range based for loop to take the value by reference so that ↵Craig Topper2017-08-301-1/+1
| | | | | | SimplifyTree can modify the copy in the array if its needs to. llvm-svn: 312088
* [Bash-autocompletion] Add support for -std=Yuka Takahashi2017-08-291-2/+2
| | | | | | | | | | | | | | | Summary: Add support for autocompleting values of -std= by including LangStandards.def. This patch relies on D36782, and is using two-stage code generation. Reviewers: v.g.vassilev, teemperor, ruiu Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D36820 llvm-svn: 311971
* Revert "Revert r311552: [Bash-autocompletion] Add support for static ↵Yuka Takahashi2017-08-291-0/+26
| | | | | | | | | | | analyzer flags" This reverts commit 7c46b80c022e18d43c1fdafb117b0c409c5a6d1e. r311552 broke lld buildbot because I've changed OptionInfos type from ArrayRef to vector. However the bug is fixed, so I'll commit this again. llvm-svn: 311958
* Try to fix compilation problem with libstdc++Matthias Braun2017-08-281-1/+3
| | | | llvm-svn: 311918
* Address r311914 review commentsMatthias Braun2017-08-281-7/+5
| | | | llvm-svn: 311917
* TableGen: Fix subreg composition/concatenationMatthias Braun2017-08-282-33/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes 2 problems in subregister hierarchies with multiple levels and tuples: 1) For bigger tuples computing secondary subregs would miss 2nd order effects. In the test case a register like `S10_S11_S12_S13_S14` with D5 = S10_S11, D6 = S12_S13 we would correctly compute sub0 = D5, sub1 = D6 but would miss the fact that we could now form ssub0_ssub1_ssub2_ssub3 (aka sub0_sub1) = D5_D6. This is fixed by changing computeSecondarySubRegs() to compute a fixpoint. 2) Fixing 1) exposed a problem where TableGen would create multiple names for effectively the same subregister index. In the test case the subregister index sub0 is composed from ssub0 and ssub1, and sub1 is composed from ssub2 and ssub3. TableGen should not create both sub0_sub1 and ssub0_ssub1_ssub2_ssub3 as infered subregister indexes. This changes the code to build a transitive closure of the subregister components before forming new concatenated subregister indexes. This fix was developed for an out of tree target. For the in-tree targets the only change is in the register information computed for ARM. There is a slight chance this fixed/improved some register coalescing around the QQQQ/QQ register classes there but I couldn't see/provoke any code generation differences. Differential Revision: https://reviews.llvm.org/D36913 llvm-svn: 311914
* TableGen: Add -gen-register-info-debug-dumpMatthias Braun2017-08-281-4/+67
| | | | | | | | | | | | | | | | | | Adds a new --gen-register-info-debug-dump mode to tablegen that dumps various register related information: - List of register classes with super and subclasses - List of subregister indexes with lanemasks - List of registers with subregisters I will use this in an upcoming commit to create a test. It may also be useful for target developers wanting to get an overview of all the register related information, esp. the things inferred by tablegen and not directly visible in the .td file. Differential Revision: https://reviews.llvm.org/D36911 llvm-svn: 311913
* [globalisel][tablegen] Predicates should start from GIPFP_Invalid+1 not ↵Daniel Sanders2017-08-241-2/+4
| | | | | | | | | GIPFP_Invalid This fixes a warning when there are zero defined predicates and also fixes an unnoticed bug where the first predicate in the table was unusable. llvm-svn: 311684
* Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-241-13/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 The previous commit was reverted for breaking the build but this appears to have been the recurring problem on the Windows bots with tablegen not being re-run when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a build with clean=True should fix it but this string should do this in advance: Requires a clean build. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311645
* Revert r311546 as it breaks buildVictor Leschuk2017-08-231-124/+13
| | | | | | http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4394 llvm-svn: 311560
* Revert r311552: [Bash-autocompletion] Add support for static analyzer flagsRui Ueyama2017-08-231-26/+0
| | | | | | This reverts commit r311552 because it broke ubsan and asan bots. llvm-svn: 311557
* [Bash-autocompletion] Add support for static analyzer flagsYuka Takahashi2017-08-231-0/+26
| | | | | | | | | | | | | | | | | | | | | | Summary: This is a patch for clang autocomplete feature. It will collect values which -analyzer-checker takes, which is defined in clang/StaticAnalyzer/Checkers/Checkers.inc, dynamically. First, from ValuesCode class in Options.td, TableGen will generate C++ code in Options.inc. Options.inc will be included in DriverOptions.cpp, and calls OptTable's addValues function. addValues function will add second argument to Option's Values class. Values contains string like "foo,bar,.." which is handed to Values class in OptTable. Reviewers: v.g.vassilev, teemperor, ruiu Subscribers: hiraditya, cfe-commits Differential Revision: https://reviews.llvm.org/D36782 llvm-svn: 311552
* [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-231-13/+124
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311546
* [globalisel][tablegen] Add tests for FeatureBitsets and ComplexPattern ↵Daniel Sanders2017-08-231-3/+6
| | | | | | predicates. llvm-svn: 311542
* [AVX512] Add 128->256 vbroadcastf64x2/vbroadcasti64x2 instructions to the ↵Craig Topper2017-08-211-0/+3
| | | | | | EVEX->VEX table. llvm-svn: 311307
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-171-33/+29
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 311084
* Re-commit: [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-171-40/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
* Revert r310919 - [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-151-100/+60
| | | | | | | | | | As expected, this failed on the windows bots but the instrumentation showed something interesting. The ADD8ri and INC8r rules are never directly compared on the windows machines. That implies that the issue lies in transitivity of the Compare predicate. I believe I've already verified that but maybe I missed something. llvm-svn: 310922
* Re-commit with some instrumentation: [globalisel][tablegen] Support ↵Daniel Sanders2017-08-151-60/+100
| | | | | | | | | | | | | | | | | | | | | | | | | zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on the windows bots and this one is likely to fail on those same bots. However, the added instrumentation should reveal a particular isHigherPriorityThan() evaluation which I'm expecting to expose that these machines are weighing priority of two rules differently from the non-windows machines. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 310919
* Revert r310716 (and r310735): [globalisel][tablegen] Support ↵Daniel Sanders2017-08-111-65/+50
| | | | | | | | | | | zero-instruction emission. Two of the Windows bots are failing test\CodeGen\X86\GlobalISel\select-inc.mir which should not have been affected by the change. Reverting while I investigate. Also reverted r310735 because it builds on r310716. llvm-svn: 310745
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-111-33/+29
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 310735
* [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-111-25/+44
| | | | | | | | | | | | | | | | | | | Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. Depends on D35833 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 310716
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