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* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-223-16/+21
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-211-13/+13
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-7/+7
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* Revert MSVC 2017 build fix and fix it by moving the method that implicitly ↵Reid Kleckner2017-10-161-32/+34
| | | | | | instantiates addPredicate out of line llvm-svn: 315932
* Fix the build of GlobalISelEmitter with MSVC 2017 by specializing earlierReid Kleckner2017-10-161-12/+12
| | | | | | | MSVC doesn't seem to like implicitly instantiating addPredicate and then explicitly specializing it later. It causes an internal compiler error. llvm-svn: 315930
* [TableGen] Simplify CallingConvEmitter.cpp. NFC.Javed Absar2017-10-161-8/+8
| | | | llvm-svn: 315911
* [TableGen] Range loopify DAGISelMatcher. NFC.Javed Absar2017-10-161-15/+15
| | | | llvm-svn: 315891
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-13/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-11/+5
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-161-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* [globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders2017-10-161-17/+105
| | | | | | | | | | | | | | | | | | | | | | | | MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
* [tablegen] Use hasPredCode()/hasImmCode() instead of ↵Daniel Sanders2017-10-152-5/+17
| | | | | | | | getPredCode().empty()/getImmCode().empty(). NFC These are cheaper ways of testing for the presence of code than generating the C++ code and testing it's empty. llvm-svn: 315872
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-151-31/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-151-99/+31
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-151-31/+99
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* [TableGen] Remove error checks incorrectly failing on non-error conditionsKrzysztof Parzyszek2017-10-151-49/+6
| | | | | | | | | | | | | In type inference, an empty type set for a specific hw mode is not an error. In earlier stages of the design it was, but having to use non- parameterized types with target intrinsics necessarily led to type contradictions: since the intrinsics used specific types, they were only valid for a specific hw mode, and the resulting type set for other modes ended up empty. To accommodate the existence of such intrinsics individual type sets were allowed to be empty as long as not all sets were empty. llvm-svn: 315858
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-153-3/+3
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFCDaniel Sanders2017-10-151-10/+33
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 llvm-svn: 315843
* [tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders2017-10-153-11/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-143-19/+18
| | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters. llvm-svn: 315826
* [globalisel][tablegen] Simplify named operand/operator lookups and fix a ↵Daniel Sanders2017-10-141-69/+128
| | | | | | | | | | | | | | | | | | | | | | wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
* [globalisel][tablegen] Fix a use-after free bug that manifests on non-macOS ↵Daniel Sanders2017-10-131-1/+1
| | | | | | machines. llvm-svn: 315765
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-133-19/+95
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 ↵Daniel Sanders2017-10-133-28/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use them. Summary: The purpose of this patch is to expose more information about ImmLeaf-like PatLeaf's so that GlobalISel can learn to import them. Previously, ImmLeaf could only be used to test int64_t's produced by sign-extending an APInt. Other tests on immediates had to use the generic PatLeaf and extract the constant using C++. With this patch, tablegen will know how to generate predicates for APInt, and APFloat. This will allow it to 'do the right thing' for both SelectionDAG and GlobalISel which require different methods of extracting the immediate from the IR. This is NFC for SelectionDAG since the new code is equivalent to the previous code. It's also NFC for FastISel because FastIselShouldIgnore is 1 for the ImmLeaf subclasses. Enabling FastIselShouldIgnore == 0 for these new subclasses will require a significant re-factor of FastISel. For GlobalISel, it's currently NFC because the relevant code to import the affected rules is not yet present. This will be added in a later patch. Depends on D36086 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: bjope, aemerson, rengolin, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36534 llvm-svn: 315747
* Revert r315148 [TableGen] Avoid unnecessary std::string creationsDaniel Sanders2017-10-132-13/+13
| | | | | | | | I'm about to commit a patch that makes them necessary for getPredCode() and it would be strange for getPredCode() and getImmCode() to require different usage. llvm-svn: 315733
* [TableGen] : Simplify RegisterInfoEmitterJaved Absar2017-10-131-6/+4
| | | | llvm-svn: 315700
* [TableGen] Allow intrinsics to have up to 8 return values.Artem Belevich2017-10-121-1/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D38633 llvm-svn: 315598
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-123-3/+3
| | | | | | | | | | | | | | | Summary: Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP. Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods. Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so it'll be picked up by public headers. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 315590
* [AsmParser] Suppress compile warning for targets with no register diagsOliver Stannard2017-10-121-11/+17
| | | | | | | This fixes the "switch statement contains 'default' but no 'case' labels" warnings in table-generated code introduced in r315295. llvm-svn: 315571
* Revert "[ADT] Make Twine's copy constructor private."Zachary Turner2017-10-111-2/+2
| | | | | | | | | | This reverts commit 4e4ee1c507e2707bb3c208e1e1b6551c3015cbf5. This is failing due to some code that isn't built on MSVC so I didn't catch. Not immediately obvious how to fix this at first glance, so I'm reverting for now. llvm-svn: 315536
* [ADT] Make Twine's copy constructor private.Zachary Turner2017-10-111-2/+2
| | | | | | | | | | | | | | | | | There's a lot of misuse of Twine scattered around LLVM. This ranges in severity from benign (returning a Twine from a function by value that is just a string literal) to pretty sketchy (storing a Twine by value in a class). While there are some uses for copying Twines, most of the very compelling ones are confined to the Twine class implementation itself, and other uses are either dubious or easily worked around. This patch makes Twine's copy constructor private, and fixes up all callsites. Differential Revision: https://reviews.llvm.org/D38767 llvm-svn: 315530
* [TableGen] Tidy up CodeGenSchedule.cppJaved Absar2017-10-111-13/+13
| | | | | | Use range_loop where it simplifies. llvm-svn: 315446
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-2/+94
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [TableGen] Convert VarDef to range_loop. NFC.Javed Absar2017-10-101-2/+2
| | | | llvm-svn: 315321
* [AsmParser] Add DiagnosticString to register classes in tablegenOliver Stannard2017-10-101-9/+68
| | | | | | | | | | | | | | | | | | | | | | | | | This allows a DiagnosticType and/or DiagnosticString to be associated with a RegisterClass in tablegen, so that we can emit diagnostics in the assembler when a register operand is incorrect. DiagnosticType creates a predictable enum value, which gets returned as the error code when an operand does not match, and can be used by the assembly parser to map to a user-facing diagnostic. DiagnosticString creates an anonymous enum value (currently based on the tablegen class name), and a function to map from enum values to strings will be generated. Both of these work the same was as they do for AsmOperand. This isn't used by any targets yet, but has one (positive) side-effect. It improves the diagnostic codes returned by validateOperandClass - we always want to emit the diagnostic that relates to the expected operand class, but this wasn't always being done when the expected and actual classes were completely different (token/register/custom). This causes a few AArch64 diagnostics to be improved, as Match_InvalidOperand was being returned instead of a specific diagnostic type. Differential revision: https://reviews.llvm.org/D36691 llvm-svn: 315295
* Fix LLDB build for Android.Eugene Zemtsov2017-10-091-1/+1
| | | | | | | | Currently libstdc++ on Android doesn't support std::to_string(). Differential Revision: https://reviews.llvm.org/D38701 llvm-svn: 315246
* [globalisel] Add support for ValueType operands in patterns.Daniel Sanders2017-10-091-1/+9
| | | | | | | | | | | | It's rare but there are a small number of patterns like this: (set i64:$dst, (add i64:$src1, i64:$src2)) These should be equivalent to register classes except they shouldn't check for a specific register bank. This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other in-tree targets such as BPF. llvm-svn: 315226
* [TableGen] remove make_range where not necessaryJaved Absar2017-10-091-6/+5
| | | | llvm-svn: 315209
* [TableGen] Simplify, add range_loop in CodeGenScheduleJaved Absar2017-10-081-11/+10
| | | | llvm-svn: 315183
* [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend ↵Ayman Musa2017-10-084-0/+671
| | | | | | | | | | | | | | | | | | | | | | | | | | while disabling it by default. After the original commit ([[ https://reviews.llvm.org/rL304088 | rL304088 ]]) was reverted, a discussion in llvm-dev was opened on 'how to accomplish this task'. In the discussion we concluded that the best way to achieve our goal (which is to automate the folding tables and remove the manually maintained tables) is: # Commit the tablegen backend disabled by default. # Proceed with an incremental updating of the manual tables - while checking the validity of each added entry. # Repeat previous step until we reach a state where the generated and the manual tables are identical. Then we can safely remove the manual tables and include the generated tables instead. # Schedule periodical (1 week/2 weeks/1 month) runs of the pass: - if changes appear (new entries): - make sure the entries are legal - If they are not, mark them as illegal to folding - Commit the changes (if there are any). CMake flag added for this purpose is "X86_GEN_FOLD_TABLES". Building with this flags will run the pass and emit the X86GenFoldTables.inc file under build/lib/Target/X86/ directory which is a good reference for any developer who wants to take part in the effort of completing the current folding tables. Differential Revision: https://reviews.llvm.org/D38028 llvm-svn: 315173
* [TableGen] Avoid repeated find calls in CodeGenDAGPatterns getters. NFCI.Simon Pilgrim2017-10-071-14/+21
| | | | | | | | The assertion tests were using count() instead of testing the find result, resulting in double the number of searches in debug/assert builds. Instead, call find once (like the release builds do) and assert the result against end(). llvm-svn: 315151
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-072-13/+13
| | | | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters and in CodeGenDAGPatterns::getSDNodeNamed Differential Revision: https://reviews.llvm.org/D38624 llvm-svn: 315148
* Strip trailing whitespaceSimon Pilgrim2017-10-062-13/+13
| | | | llvm-svn: 315070
* [TableGen] Simplify SubtargetEmitterJaved Absar2017-10-061-8/+4
| | | | | | Remove unnecessary duplicate if-condition. llvm-svn: 315068
* [TableGen] : CodeGenInsrtuction modify to range loop. NFC.Javed Absar2017-10-061-2/+2
| | | | llvm-svn: 315050
* [TablgeGen] : Tidy up CodeGenSchedule. NFC.Javed Absar2017-10-051-25/+21
| | | | | | | Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38534 llvm-svn: 314982
* [AsmParser] Add DiagnosticString to AsmOperands in tablegenOliver Stannard2017-10-031-2/+47
| | | | | | | | | | | | | | This adds a DiagnosticString member to the AsmOperand tablegen class, so that the diagnostic text to be used when an assembly operand is incorrect can be stored in the tablegen description of the operand, rather than in a separate switch statement in the AsmParser. If DiagnosticString is used for any operands, tablegen will emit a getMatchKindDiag function, to map from diagnostic enums to strings. Differential revision: https://reviews.llvm.org/D31606 llvm-svn: 314803
* [Assembler] Report multiple near misses for invalid instructionsOliver Stannard2017-10-031-66/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current table-generated assembly instruction matcher returns a 64-bit error code when matching fails. Since multiple instruction encodings with the same mnemonic can fail for different reasons, it uses some heuristics to decide which message is important. This heuristic does not work well for targets that have many encodings with the same mnemonic but different operands, or which have different versions of instructions controlled by subtarget features, as it is hard to know which encoding the user was intending to use. Instead of trying to improve the heuristic in the table-generated matcher, this patch changes it to report a list of near-miss encodings. This list contains an entry for each encoding with the correct mnemonic, but with exactly one thing preventing it from being valid. This thing could be a single invalid operand, a missing target feature or a failed target-specific validation function. The target-specific assembly parser can then report an error message giving multiple options for instruction variants that the user may have been trying to use. For example, I am working on a patch to use this for ARM, which can give this error for an invalid instruction for ARMv6-M: <stdin>:8:3: error: invalid instruction, multiple near-miss encodings found adds r0, r1, #0x8 ^ <stdin>:8:3: note: for one encoding: instruction requires: thumb2 adds r0, r1, #0x8 ^ <stdin>:8:16: note: for one encoding: expected an integer in range [0, 7] adds r0, r1, #0x8 ^ <stdin>:8:16: note: for one encoding: expected a register in range [r0, r7] adds r0, r1, #0x8 ^ This also allows the target-specific assembly parser to apply its own heuristics to suppress some errors. For example, the error "instruction requires: arm-mode" is never going to be useful when targeting an M-profile architecture (which does not have ARM mode). This patch just adds the target-independent mechanism for doing this, all targets still use the old mechanism. I've added a bit in the AsmParser tablegen class to allow targets to switch to this new mechanism. To use this, the target-specific assembly parser will have to be modified for the change in signature of MatchInstructionImpl, and to report errors based on the list of near-misses. Differential revision: https://reviews.llvm.org/D27620 llvm-svn: 314774
* Cleanup some problems with LLVM_ENABLE_DUMP in release builds, andDon Hinton2017-09-271-1/+1
| | | | | | | | always set LLVM_ENABLE_DUMP=ON for +Asserts builds. Differential Revision: https://reviews.llvm.org/D38306 llvm-svn: 314346
* Use const where possible. NFCI.Simon Pilgrim2017-09-271-1/+1
| | | | llvm-svn: 314292
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