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* Revert r318822 "[llvm-tblgen] - Stop using std::string in RecordKeeper."George Rimar2017-11-231-4/+5
| | | | | | It reported to have problems with memory sanitizers and DBUILD_SHARED_LIBS=ON. llvm-svn: 318899
* [llvm-tblgen] - Stop using std::string in RecordKeeper.George Rimar2017-11-221-5/+4
| | | | | | | | | | | RecordKeeper::getDef() is a hot place, it shows up in profiling and it creates std::string instance for each search in RecordMap though RecordKeeper::RecordMap can use StringRef as a key instead to avoid that. Patch do that change. Differential revision: https://reviews.llvm.org/D40170 llvm-svn: 318822
* [SelectionDAG] Add a isel matcher op to check the type of node results other ↵Craig Topper2017-11-221-5/+8
| | | | | | | | than result 0. I plan to use this to check the type of the mask result of masked gathers in the X86 backend. llvm-svn: 318820
* [TableGen] Improve error reportingEvandro Menezes2017-11-213-14/+19
| | | | | | | | | When searching for a resource unit, use the reference location instead of the definition location in case of an error. Differential revision: https://reviews.llvm.org/D40263 llvm-svn: 318803
* [Asm] Improve "too few operands" errorsOliver Stannard2017-11-211-1/+1
| | | | | | | | | | - We can still emit this error if the actual instruction has two or more operands missing compared to the expected one. - We should only emit this error once per instruction. Differential revision: https://reviews.llvm.org/D36746 llvm-svn: 318770
* [Asm] Finish matching once end of formal and actual lists reached (NFC)Oliver Stannard2017-11-211-0/+1
| | | | | | | | | | This is NFC, as the matcher would continue looping up to the maximum number of operands with no effect, but this should improve performance a bit, and makes the debug trace clearer. Differential revision: https://reviews.llvm.org/D36744 llvm-svn: 318769
* Revert r318759 due to make check-all failure on WindowsSander de Smalen2017-11-211-2/+3
| | | | llvm-svn: 318768
* [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-11-211-3/+2
| | | | | | | | | | | | | | | | | Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 318759
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-2/+15
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 llvm-svn: 318650
* [globalisel][tablegen] Generalize pointer-type inference by introducing ↵Daniel Sanders2017-11-183-4/+18
| | | | | | | | | | | | | | | ptypeN. NFC ptypeN is functionally the same as typeN except that it informs the SelectionDAG importer that an operand should be treated as a pointer even if it was written as iN. This is important for patterns that use iN instead of iPTR to represent pointers. E.g.: (set GPR64:$dst, (load GPR64:$addr)) Previously, this was handled as a hardcoded special case for the appropriate operands to G_LOAD and G_STORE. llvm-svn: 318574
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-172-2/+2
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [globalisel][tablegen] Generate rule coverage and use it to identify ↵Daniel Sanders2017-11-161-4/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
* [Docs] Add tablegen backend for target opcode documentationOliver Stannard2017-11-144-0/+240
| | | | | | | | | | This is a tablegen backend to generate documentation for the opcodes that exist for each target. For each opcode, it lists the assembly string, the names and types of all operands, and the flags and predicates that apply to the opcode. Differential revision: https://reviews.llvm.org/D31025 llvm-svn: 318155
* [tablegen] Handle atomic predicates for ordering inside tablegen. NFC.Daniel Sanders2017-11-132-1/+64
| | | | | | | | | | | | | | | | Similar to r315841, GlobalISel and SelectionDAG require different code for the common atomic predicates due to differences in the representation. Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common atomic predicates related to ordering into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. llvm-svn: 318102
* [tablegen] Handle atomic predicates for memory type inside tablegen. NFC.Daniel Sanders2017-11-132-12/+33
| | | | | | | | | | | | | | | | Similar to r315841, GlobalISel and SelectionDAG require different code for the common atomic predicates due to differences in the representation. Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common atomic predicates related to memory type into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. llvm-svn: 318095
* [globalisel][tablegen] Add support for extload.Daniel Sanders2017-11-131-6/+12
| | | | llvm-svn: 318068
* fix printing of alias instructions by removing redundant spacingPetar Jovanovic2017-11-131-1/+3
| | | | | | | | | | | | Some alias instructions are printed with an extra space after the tab character. Fix this by skipping that space when the tab character is printed so that the instructions are aligned with the rest of the code. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35946 llvm-svn: 318059
* [globalisel][tablegen] Import signextload and zeroextload.Daniel Sanders2017-11-113-5/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. llvm-svn: 317971
* Allow separation of declarations and definitions in <Target>ISelDAGToDAG.incKrzysztof Parzyszek2017-11-102-17/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to include the member function declarations in the instruction selector class separately from the member bodies. Defining GET_DAGISEL_DECL macro to any value will only include the member declarations. To include bodies, define GET_DAGISEL_BODY macro to be the selector class name. Example: class FooDAGToDAGISel : public SelectionDAGISel { // Pull in declarations only. #define GET_DAGISEL_DECL #include "FooISelDAGToDAG.inc" }; // Include the function bodies (with names qualified with the provided // class name). #define GET_DAGISEL_BODY FooDAGToDAGISel #include "FooISelDAGToDAG.inc" When neither of the two macros are defined, the function bodies are emitted inline (in the same way as before this patch). Differential Revision: https://reviews.llvm.org/D39596 llvm-svn: 317903
* [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish ↵Florian Hahn2017-11-071-0/+5
| | | | | | | | | | | | | | | Scalable Vectors Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39087 llvm-svn: 317564
* Move the llvm-tblgen project into the Tablegenning folder on IDEs like ↵Aaron Ballman2017-11-041-0/+1
| | | | | | Visual Studio rather than leave it in the root directory. NFC. llvm-svn: 317420
* [X86] Teach EVEX->VEX pass to turn SHUFI32X4/SHUFF32X4/SHUFI64X/SHUFF64X2 ↵Craig Topper2017-11-041-0/+8
| | | | | | | | into VPERM2F128/VPERM2I128. This recovers some of the tests that were changed by r317403. llvm-svn: 317410
* [globalisel][tablegen] Skip src child predicatesDiana Picus2017-11-031-0/+3
| | | | | | | | | | | | | | | | | | The GlobalISel TableGen backend didn't check for predicates on the source children. This caused it to generate code for ARM patterns such as SMLABB or similar, but without properly checking for the sext_16_node part of the operands. This in turn meant that we would select SMLABB instead of MLA for simple sequences such as s32 + s32 * s32, which is wrong (we want a MLA on the full operands, not just their bottom 16 bits). This patch forces TableGen to skip patterns with predicates on the src children, so it doesn't generate code for SMLABB and other similar ARM instructions at all anymore. AArch64 and X86 are not affected. Differential Revision: https://reviews.llvm.org/D39554 llvm-svn: 317313
* [TableGen] Add an extra blank line to DAGISel output file to separate functions.Craig Topper2017-11-031-1/+1
| | | | llvm-svn: 317298
* [globalisel][regbank] Warn about MIR ambiguities when register bank/class ↵Daniel Sanders2017-11-011-0/+13
| | | | | | names clash. llvm-svn: 317132
* [X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit ↵Craig Topper2017-11-011-1/+7
| | | | | | | | | | VPALIGND/Q into VPALIGNR if the extended registers aren't being used. This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding. Differential Revision: https://reviews.llvm.org/D39401 llvm-svn: 317122
* [globalisel][tablegen] Add support for multi-insn emissionDaniel Sanders2017-11-011-9/+129
| | | | | | | | | | | | | | The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
* Fix warnings discovered by rL317076. [-Wunused-private-field]NAKAMURA Takumi2017-11-011-2/+1
| | | | llvm-svn: 317091
* [globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFCDaniel Sanders2017-11-011-23/+27
| | | | | | | The next commit will add support for multi-instruction emission so we need to start allocating instruction ID's instead of hard-coding them to 0. llvm-svn: 317057
* Re-commit: [globalisel][tablegen] Keep track of the insertion point while ↵Daniel Sanders2017-10-311-32/+73
| | | | | | | | | | | | | | | | | | | adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
* Revert r317040: [globalisel][tablegen] Keep track of the insertion point ↵Daniel Sanders2017-10-311-77/+33
| | | | | | | | | | while adding BuildMIAction's. NFC The same bots fail but I believe I know what the issue is now. These bots are missing the const_iterator versions of insert/emplace/etc. that were introduced in C++11. llvm-svn: 317042
* Re-commit: [globalisel][tablegen] Keep track of the insertion point while ↵Daniel Sanders2017-10-311-33/+77
| | | | | | | | | | | | | | | | | | | adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots didn't like a call to emplace(). I've replaced it with insert() to see if it's a quirk of the C++11 support. llvm-svn: 317040
* Revert r317029: [globalisel][tablegen] Keep track of the insertion point ↵Daniel Sanders2017-10-311-77/+33
| | | | | | | | while adding BuildMIAction's. NFC The Linux bots don't seem to like this usage of emplace(). Reverting while I look into it. llvm-svn: 317033
* [globalisel][tablegen] Keep track of the insertion point while adding ↵Daniel Sanders2017-10-311-33/+77
| | | | | | | | | | | | | | | BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. llvm-svn: 317029
* [globalisel][tablegen] Factor out implicit def/use renderers from ↵Daniel Sanders2017-10-311-12/+48
| | | | | | | | | | | | createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
* [globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction ↵Daniel Sanders2017-10-311-43/+73
| | | | | | | | | | | | | | | | | | to choose a mutatable instruction. NFC Prepare for multiple instruction emission by allowing BuildMIAction to search for a suitable matcher that will support mutation. This patch deliberately neglects to add matchers aside from the root to preserve NFC. That said, it should be noted that until we support mutations other than just the opcode the chances of finding a non-root instruction for which canMutate() is true, is essentially zero. Furthermore in the presence of multi-instruction emission the chances of finding any instruction for which canMutate() is true is also zero. Nevertheless, we can't continue to require that all BuildMIAction's consider the root of the match to be recyclable due to the risk of recycling it twice in the same rule. llvm-svn: 317022
* [globalisel][tablegen] Allow any comment in DebugCommentAction. NFCDaniel Sanders2017-10-311-6/+6
| | | | llvm-svn: 317017
* [TableGen] Use Twine instead of std::string concatenation in two calls to ↵Craig Topper2017-10-261-4/+4
| | | | | | PrintFatalError. llvm-svn: 316697
* [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell ↵Craig Topper2017-10-261-5/+15
| | | | | | | | check function so it can use the correct table based on variant. I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants. llvm-svn: 316641
* [AsmParser][TableGen] Make the generated mnemonic spell checker function a ↵Craig Topper2017-10-261-3/+9
| | | | | | | | file local static function. Also only emit in targets that specificially request it. This is required so we don't get an unused static function error. llvm-svn: 316640
* [globalisel][tablegen] Fix future undefined behaviour in r316463.Daniel Sanders2017-10-241-1/+4
| | | | | | | I missed a dereference of `Matched` that preceeded the new check. Thanks to Justin Bogner for spotting it. llvm-svn: 316480
* [globalisel][tablegen] Multi-insn emission requires that BuildMIAction ↵Daniel Sanders2017-10-241-6/+6
| | | | | | | | | | | support not being linked to an InstructionMatcher. NFC When multi-instruction emission is supported, it will no longer be guaranteed that every BuildMIAction has a corresponding matched instruction. BuildMIAction should support not having one to cover the case where a rule produces more instructions than it matched. llvm-svn: 316463
* [TableGen] Fix some formatting quirks in the subtarget output file.Craig Topper2017-10-241-4/+5
| | | | llvm-svn: 316450
* [TableGen] Simplify some of the subtarget emission by removing code that ↵Craig Topper2017-10-241-45/+11
| | | | | | | | avoids printing commas at the end of arrays and enums. The C++ standard allows for trailing commas. We already do this in many other emitters. llvm-svn: 316449
* [globalisel][tablegen] Remove unused InstructionMatcher's. NFCDaniel Sanders2017-10-241-25/+12
| | | | llvm-svn: 316407
* [globalisel][tablegen] Import stores and allow GISel to automatically ↵Daniel Sanders2017-10-231-1/+79
| | | | | | | | | | | | | | | | | substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
* [X86] Fix disassembler table generation to prevent instructions tagged with ↵Craig Topper2017-10-233-16/+20
| | | | | | 'PS' being inherited into PD/XS/XD attribute entries. llvm-svn: 316345
* [X86] Update a doxygen comment in the disassembler tablegen code. NFCCraig Topper2017-10-231-0/+1
| | | | llvm-svn: 316309
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-233-57/+161
| | | | | | Fixes PR31955. llvm-svn: 316308
* [X86] More correctly support LIG and WIG for EVEX instructions in the ↵Craig Topper2017-10-221-74/+168
| | | | | | | | | | disassembler tables. This is similar to how we generate the VEX tables. More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding). llvm-svn: 316294
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