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* [TableGen] Return ArrayRef instead of a std::vector reference from ↵Craig Topper2016-01-173-19/+19
| | | | | | getInstructionsByEnumValue(). NFC llvm-svn: 258018
* [TableGen] Use std::find instead of a manual loop. NFCCraig Topper2016-01-171-3/+1
| | | | llvm-svn: 258017
* [TableGen] Use a StringRef instead of creating a new std::string. It gets ↵Craig Topper2016-01-171-3/+2
| | | | | | passed to a function that takes a StringRef anyway. NFC llvm-svn: 258007
* [TableGen] Changes to AsmWriterEmitter to remove the CodeGenInstruction to ↵Craig Topper2016-01-173-70/+49
| | | | | | | | AsmWriterInst map. NFC Adds the corresponding CodeGenInstruction number to each AsmWriterInst. Then write all the operand uniqueing loops using the AsmWriterInst array and indices. Then use the CodeGenInstruction index to fill out the OpCodeInfo array. llvm-svn: 258005
* [TableGen] Use std::find instead of a manual loop. NFCCraig Topper2016-01-171-10/+8
| | | | llvm-svn: 258004
* [TableGen] Pass PassSubtarget flag into getCode instead of storing a copy of ↵Craig Topper2016-01-143-32/+25
| | | | | | the flag in every AsmWriterOperand. NFC llvm-svn: 257743
* [TableGen] Cleanup output formatting and add llvm_unreachables to the output ↵Craig Topper2016-01-131-5/+6
| | | | | | the AsmMatcher uses when it overflows the 64-bit tables. No in tree targets use this code, but I tested it with an temporarily reduced table width. llvm-svn: 257583
* [TableGen] Replace some hardcoded assumptions that the OpcodeInfo table is ↵Craig Topper2016-01-131-8/+10
| | | | | | 64-bits for cleanliness. NFC llvm-svn: 257582
* [TableGen] Use std::remove_if instead of an n^2 loop. NFCCraig Topper2016-01-131-8/+5
| | | | llvm-svn: 257581
* [TableGen] Fix up some stale comments in the AsmMatcher. NFCCraig Topper2016-01-131-4/+2
| | | | llvm-svn: 257580
* [TableGen] Move calls to getValueAsInt out of a loop since they aren't ↵Craig Topper2016-01-131-2/+3
| | | | | | simple functions. NFC llvm-svn: 257579
* [TableGen] Allow asm writer to use up to 3 OpInfo tables instead of 2. This ↵Craig Topper2016-01-111-30/+32
| | | | | | | | allows x86 to use 56 total bits made up of a 32-bit, 16-bit, and 8-bit table. Previously we were using 64 total bits. This saves 14K from the x86 table size. And saves space on other targets as well. llvm-svn: 257315
* [TableGen] Remove unnecessary 0 terminator from an array that only existed ↵Craig Topper2016-01-111-4/+0
| | | | | | to prevent ending an array with a comma. But that's perfectly legal and not something we need to prevent. NFC llvm-svn: 257314
* [TableGen] Remove a few spaces from AsmMatcher output. NFCCraig Topper2016-01-111-3/+3
| | | | llvm-svn: 257308
* [TableGen] Use range-based for loops. Also fix one loop to not use some ↵Craig Topper2016-01-081-25/+20
| | | | | | index name as an outer loop. NFC llvm-svn: 257156
* [TableGen] Combine variable declaration and initialization. Move a string ↵Craig Topper2016-01-081-3/+2
| | | | | | into a vector instead of copying. NFC llvm-svn: 257155
* [TableGen] Call llvm_shutdown on exit so that all the ManagedStatic objects ↵Craig Topper2016-01-041-0/+3
| | | | | | in the support library will be deleted. llvm-svn: 256732
* [TableGen] Simplify some code slightly. No need to check if the arrays are ↵Craig Topper2016-01-031-18/+10
| | | | | | empty before printing. The loop can be made to print the same thing if the loop is empty. NFC llvm-svn: 256703
* [TableGen] Replace a logically negated xor of bools with just an equality ↵Craig Topper2016-01-031-1/+1
| | | | | | comparison for readability. NFC llvm-svn: 256699
* [TableGen] Use std::find_if and a lambda instead of manual loops.Craig Topper2016-01-031-9/+10
| | | | llvm-svn: 256698
* [TableGen] Fix a bug introduced in r256627. If the switch was not emitted we ↵Craig Topper2016-01-031-2/+3
| | | | | | still emitted a closing curly brace. llvm-svn: 256697
* [TableGen] Use range-based for loops. NFCCraig Topper2016-01-031-20/+13
| | | | llvm-svn: 256696
* [TableGen] Modify the AsmMatcherEmitter to only apply the table growth from ↵Craig Topper2015-12-311-63/+110
| | | | | | | | | | | | | | r252440 to the Hexagon target. This restores the previous behavior of not including the mnemonic in the classes table for every target that starts instruction lines with the mnemonic. Not only did the table size increase by 1 entry, but the class enum increased in size which caused every class in the array to increase in size. It also grew the size of the function that parsers tokens into classes by a substantial amount. This adds a new HasMnemonicFirst flag to all AsmParsers. It's set to 1 by default and Hexagon target overrides it to 0. For the X86 target alone this recovers 324KB of size on the llvm-mc executable. I believe the current state is still a bad design choice for the Hexagon target as it causes most of the parsing to do a linear search through the entire match table to comparing operands against every instruction until it finds one that works. At least for the other targets we do a binary search based on mnemonic over which to do the linear scan. llvm-svn: 256669
* [TableGen] Use range-based for loops. NFCCraig Topper2015-12-311-8/+3
| | | | llvm-svn: 256668
* [TableGen] Move determination of IsIsolatedToken into the tokenizer instead ↵Craig Topper2015-12-311-31/+33
| | | | | | of trying to search characters around the token. No functional change intended. Verified for in-tree targets. llvm-svn: 256660
* [TableGen] Remove unnecessary conversion from StringRef to std::string when ↵Craig Topper2015-12-301-2/+2
| | | | | | outputting to a raw_ostream. NFC llvm-svn: 256628
* [TableGen] Remove raw_string_ostream by just emitting the header for the ↵Craig Topper2015-12-301-20/+20
| | | | | | switch the first time we emit a case. If the header was never emitted just print the default at the end. NFC llvm-svn: 256627
* [TableGen] Use range-based for loops. NFCCraig Topper2015-12-301-4/+4
| | | | llvm-svn: 256626
* [TableGen] Move more things that come from variant into the AsmVariantInfo ↵Craig Topper2015-12-301-12/+12
| | | | | | class so we can reduce some parameters. NFC llvm-svn: 256625
* [TableGen] Use 'size_t' instead of 'unsigned' to better match the argument ↵Craig Topper2015-12-301-5/+5
| | | | | | types of addAsmOperand. Simplify some code by using StringRef::find instead of std::find. These were previously done in r247527 and r247528, but another commit seems to have erased them. NFC llvm-svn: 256624
* De-virtualize mnemonicIsValid and remove from the base class. It's not ↵Craig Topper2015-12-291-1/+1
| | | | | | called by any common code. llvm-svn: 256544
* [TableGen] Add missing space to output.Craig Topper2015-12-291-1/+1
| | | | llvm-svn: 256540
* [TableGen] Use range-based for loops. NFCCraig Topper2015-12-291-10/+5
| | | | llvm-svn: 256539
* [X86][PKU] Add {RD,WR}PKRU encodingAsaf Badouh2015-12-241-6/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D15711 llvm-svn: 256366
* Provide a way to specify inliner's attribute compatibility and merging.Akira Hatanaka2015-12-221-1/+98
| | | | | | | | | | | | | | | | | | | | | This reapplies r256277 with two changes: - In emitFnAttrCompatCheck, change FuncName's type to std::string to fix a use-after-free bug. - Remove an unnecessary install-local target in lib/IR/Makefile. Original commit message for r252949: Provide a way to specify inliner's attribute compatibility and merging rules using table-gen. NFC. This commit adds new classes CompatRule and MergeRule to Attributes.td, which are used to generate code to check attribute compatibility and merge attributes of the caller and callee. rdar://problem/19836465 llvm-svn: 256304
* Add an OperandNamespace field to Target.td's Operand.Dan Gohman2015-12-221-0/+1
| | | | | | | | For targets to add their own operand types as needed, as advertised in Operand's comment, they need to be able to specify an alternate namespace for OperandType names too. This matches the RegisterOperand class. llvm-svn: 256299
* Revert r256277 and r256279.Akira Hatanaka2015-12-221-97/+0
| | | | | | Some of the bots failed again. llvm-svn: 256280
* Provide a way to specify inliner's attribute compatibility and merging.Akira Hatanaka2015-12-221-0/+97
| | | | | | | | | | | | | | | | | | This reapplies r252990 and r252949. I've added member function getKind to the Attr classes which returns the enum or string of the attribute. Original commit message for r252949: Provide a way to specify inliner's attribute compatibility and merging rules using table-gen. NFC. This commit adds new classes CompatRule and MergeRule to Attributes.td, which are used to generate code to check attribute compatibility and merge attributes of the caller and callee. rdar://problem/19836465 llvm-svn: 256277
* [X86] Part 2 to fix x86-64 fp128 calling convention.Chih-Hung Hsieh2015-12-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | Part 1 was submitted in http://reviews.llvm.org/D15134. Changes in this part: * X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class. * X86CallingConv.td: Pass f128 values in XMM registers or on stack. * X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td: Add instruction selection patterns for f128. * X86ISelLowering.cpp: When target has MMX registers, configure MVT::f128 in FR128RegClass, with TypeSoftenFloat action, and custom actions for some opcodes. Add missed cases of MVT::f128 in places that handle f32, f64, or vector types. Add TODO comment to support f128 type in inline assembly code. * SelectionDAGBuilder.cpp: Fix infinite loop when f128 type can have VT == TLI.getTypeToTransformTo(Ctx, VT). * Add unit tests for x86-64 fp128 type. Differential Revision: http://reviews.llvm.org/D11438 llvm-svn: 255558
* [TableGen] Correct Namespace lookup with AltNames in AsmWriterEmitterHal Finkel2015-12-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | AsmWriterEmitter will generate a getRegisterName function with an alternate register name index as its second argument if the target makes use of them. The enum of these values is generated in RegisterInfoEmitter. The getRegisterName generator would assume the namespace could always be found by reading index 1 of the list of AltNameIndices, but this will fail if this list is sorted such that the NoRegAltName is at index 1. Because this list is sorted by record name (in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically before NoRegAltName. For example, if a target has something like def AnAltNameIndex : RegAltNameIndex and defines RegAltNameIndices for some registers then, prior to this change, AsmWriterEmitter would generate references to ::AnAltNameIndex and ::NoRegAltName Patch by Alex Bradbury! llvm-svn: 255344
* Use make_range to reduce mentions of iterator type. NFCCraig Topper2015-12-062-7/+5
| | | | llvm-svn: 254872
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-051-1/+1
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* [TableGen] Remove an assumption about the order of encodings in the ↵Craig Topper2015-12-031-2/+13
| | | | | | MVT::SimpleValueType enum. Instead of assuming the types are sorted by size, scan the typeset arrays to find the smallest/largest type. NFC llvm-svn: 254589
* [AArch64] Add ARMv8.2-A Statistical Profiling ExtensionOliver Stannard2015-12-011-5/+7
| | | | | | | | | | | | The Statistical Profiling Extension is an optional extension to ARMv8.2-A. Since it is an optional extension, I have added the FeatureSPE subtarget feature to control it. The assembler-visible parts of this extension are the new "psb csync" instruction, which is equivalent to "hint #17", and a number of system registers. Differential Revision: http://reviews.llvm.org/D15021 llvm-svn: 254401
* [TableGen] Use SmallString instead of std::string to build up a string to ↵Craig Topper2015-11-281-2/+3
| | | | | | avoid heap allocations. NFC llvm-svn: 254221
* [TableGen] Sort pattern predicates before concatenating into a string so ↵Craig Topper2015-11-271-4/+11
| | | | | | that different orders of the same set will produce the same string. This can reduce the number of unique predicates in the isel tables. NFC llvm-svn: 254192
* [SelectionDAG] Add a SDTCisSameSizeAs type constraint that can be used to ↵Craig Topper2015-11-262-1/+73
| | | | | | ensure vector widths match even if the element size and count don't. llvm-svn: 254138
* [TableGen] Flip reversed comments.Craig Topper2015-11-261-2/+2
| | | | llvm-svn: 254136
* Add vector types for intrinsicsKrzysztof Parzyszek2015-11-241-1/+5
| | | | | Author: Ron Lieberman <ronl@codeaurora.org> llvm-svn: 253992
* Add names for the new vector types in CodeGenTarget.cppKrzysztof Parzyszek2015-11-241-0/+9
| | | | llvm-svn: 253989
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