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* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-3/+8
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND ↵Craig Topper2011-09-141-5/+0
| | | | | | from being recognized by disassembler. llvm-svn: 139691
* Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper2011-09-131-3/+1
| | | | | | being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. llvm-svn: 139588
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-1/+1
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP ↵Craig Topper2011-09-111-1/+2
| | | | | | disassembling to ignore OpSize and REX.W. llvm-svn: 139484
* Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.Kevin Enderby2011-09-021-2/+5
| | | | llvm-svn: 139014
* Add vvvv support to disassembling of instructions with MRMDestMem and ↵Craig Topper2011-08-301-4/+27
| | | | | | MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. llvm-svn: 138795
* Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217Kevin Enderby2011-08-291-2/+3
| | | | llvm-svn: 138771
* Unconstify InitsDavid Greene2011-07-291-3/+3
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-3/+3
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-271-0/+2
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
* Make the disassembler able to disassemble a bunch of instructions with names ↵Eli Friedman2011-07-161-1/+25
| | | | | | in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. llvm-svn: 135337
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-3/+3
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-3/+3
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-1/+17
| | | | llvm-svn: 128826
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-48/+177
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-221-1/+3
| | | | | | Patch by Jai Menon. llvm-svn: 126165
* In Thumb2, direct branches can be encoded as either a "short" conditional ↵Owen Anderson2010-12-131-0/+1
| | | | | | | | | | branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. llvm-svn: 121710
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-3/+3
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* Added the x86 instruction ud2b (2nd official undefined instruction).Kevin Enderby2010-10-271-1/+0
| | | | llvm-svn: 117485
* Fixed the disassembler to handle two new X86Sean Callanan2010-10-041-1/+16
| | | | | | | instruction forms. Now the ENTER instruction disassembles correctly. llvm-svn: 115573
* Massive rewrite of MMX: Dale Johannesen2010-09-301-6/+0
| | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
* add basic avx support to the disassembler, also teach it about ssmem/sdmemChris Lattner2010-09-291-0/+6
| | | | | | | | | | operands. With this done, we can remove the _Int suffixes from the round instructions without the disassembler blowing up. This allows the assembler to support them, implementing rdar://8456376 - llvm-mc rejects 'roundss' llvm-svn: 115019
* Add patterns for MMX that use the new intrinsics.Dale Johannesen2010-09-071-1/+7
| | | | | | | Enable palignr intrinsic. These may need adjustment for a new VT in due course. llvm-svn: 113233
* Convert some tab stops into spaces.Duncan Sands2010-07-121-1/+1
| | | | llvm-svn: 108130
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-071-0/+2
| | | | | | | in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
* More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)Bruno Cardoso Lopes2010-06-111-1/+8
| | | | | | Introduce the VEX_X field llvm-svn: 105859
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-1/+7
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-7/+1
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-1/+7
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honorDaniel Dunbar2010-05-201-0/+4
| | | | | | it. llvm-svn: 104270
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-4/+2
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Fixed a bug where the disassembler would allow an immediateSean Callanan2010-04-071-1/+1
| | | | | | | | | argument that had to be between 0 and 7 to have any value, firing an assert later in the AsmPrinter. Now, the disassembler rejects instructions with out-of-range values for that immediate. llvm-svn: 100694
* Check in tablegen changes to fix disassembler related failures caused by r98465.Evan Cheng2010-03-141-0/+1
| | | | llvm-svn: 98468
* Changed the table generator so that the X86Sean Callanan2010-02-241-3/+4
| | | | | | disassembler never recognizes InitReg instructions. llvm-svn: 97017
* Added the rdtscp instruction to the x86 instructionSean Callanan2010-02-131-1/+2
| | | | | | tables. llvm-svn: 96073
* Fixed encodings for invlpg, invept, and invvpid.Sean Callanan2010-02-131-32/+7
| | | | llvm-svn: 96065
* remove special cases for vmlaunch, vmresume, vmxoff, and swapgsChris Lattner2010-02-131-8/+8
| | | | | | fix swapgs to be spelled right. llvm-svn: 96058
* Remove special cases for [LM]FENCE, MONITOR and MWAIT fromChris Lattner2010-02-121-3/+0
| | | | | | encoder and decoder by using new MRM_ forms. llvm-svn: 96048
* Reworked the Intel disassembler to support instructionsSean Callanan2010-02-121-17/+51
| | | | | | | | | | | | whose opcodes extend into the ModR/M field using the Form field of the instruction rather than by special casing each instruction. Commented out the special casing of VMCALL, which is the first instruction to use this special form. While I was in the neighborhood, added a few comments for people modifying the Intel disassembler. llvm-svn: 96043
* add a bunch of mod/rm encoding types for fixed mod/rm bytes.Chris Lattner2010-02-121-2/+3
| | | | | | | This will work better for the disassembler for modeling things like lfence/monitor/vmcall etc. llvm-svn: 95960
* Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner2010-02-101-7/+4
| | | | | | | | | for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). llvm-svn: 95753
* Fixes to the X86 disassembler:Sean Callanan2009-12-221-3/+3
| | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
* Add missing newlines at EOF (for clang++).Daniel Dunbar2009-12-191-1/+1
| | | | llvm-svn: 91756
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-0/+959
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
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