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path: root/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
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* [X86] Add the ability to force an EVEX2VEX mapping table entry from the .td ↵Craig Topper2018-06-191-71/+30
| | | | | | | | | | | | | | files. Remove remaining manual table entries from the tablegen emitter. This adds an EVEX2VEXOverride string to the X86 instruction class in X86InstrFormats.td. If this field is set it will add manual entry in the EVEX->VEX tables that doesn't check the encoding information. Then use this mechanism to map VMOVDU/A8/16, 128-bit VALIGN, and VPSHUFF/I instructions to VEX instructions. Finally, remove the manual table from the emitter. This has the bonus of fully sorting the autogenerated EVEX->VEX tables by their EVEX instruction enum value. We may be able to use this to do a binary search for the conversion and get rid of the need to create a DenseMap. llvm-svn: 335018
* [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have ↵Craig Topper2018-06-191-71/+25
| | | | | | | | | | | | | | VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. EVEX makes heavy use of the VEX.W bit to indicate 64-bit element vs 32-bit elements. Many of the VEX instructions were split into 2 versions with different masking granularity. The EVEX->VEX table generate can collapse the two versions if the VEX version uses is tagged as VEX_WIG. But if the VEX version is instead marked VEX.W==0 we can't combine them because we don't know if there is also a VEX version with VEX.W==1. This patch adds a new VEX_W1X tag that indicates the EVEX instruction encodes with VEX.W==1, but is safe to convert to a VEX instruction with VEX.W==0. This allows us to remove a bunch of manual EVEX->VEX table entries. We may want to look into splitting up the VEX_WPrefix field which would simplify the disassembler. llvm-svn: 335017
* [X86] Encode the EVEX2VEX exception list information in .td files instead of ↵Craig Topper2018-06-181-26/+2
| | | | | | | | the emitter source. Rather than having an exclusion list in tablegen sources, add a flag to the X86 instruction records that can be used to suppress checking for convertibility. llvm-svn: 334971
* [X86] Add 'Z' to the internal names of various EVEX instructions for overall ↵Craig Topper2018-06-151-8/+8
| | | | | | consistency. llvm-svn: 334785
* [X86] Remove unnecessary include from one of the tblgen emitters.Craig Topper2018-06-121-1/+0
| | | | llvm-svn: 334530
* Don't repeatedly evaluate size() in the for loop. NFCI.Simon Pilgrim2018-04-111-1/+1
| | | | llvm-svn: 329853
* [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and ↵Craig Topper2018-03-221-4/+4
| | | | | | | | | | VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD This makes the Y position consistent with other instructions. This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary. llvm-svn: 328254
* [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of ↵Craig Topper2018-02-131-1/+19
| | | | | | | | | | the immediate are 0 and the regular EVEX->VEX checks pass. Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND. Fixes PR36246 llvm-svn: 324985
* [X86] Teach EVEX->VEX pass to turn SHUFI32X4/SHUFF32X4/SHUFI64X/SHUFF64X2 ↵Craig Topper2017-11-041-0/+8
| | | | | | | | into VPERM2F128/VPERM2I128. This recovers some of the tests that were changed by r317403. llvm-svn: 317410
* [X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit ↵Craig Topper2017-11-011-1/+7
| | | | | | | | | | VPALIGND/Q into VPALIGNR if the extended registers aren't being used. This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding. Differential Revision: https://reviews.llvm.org/D39401 llvm-svn: 317122
* [AVX512] Add 128->256 vbroadcastf64x2/vbroadcasti64x2 instructions to the ↵Craig Topper2017-08-211-0/+3
| | | | | | EVEX->VEX table. llvm-svn: 311307
* Another instance where GCC doesn't understand implicit construction of ↵Benjamin Kramer2017-03-241-2/+2
| | | | | | StringLiteral. llvm-svn: 298703
* Make GCC happy again.Benjamin Kramer2017-03-241-1/+1
| | | | llvm-svn: 298702
* Don't build up std::vectors with constant sizes when an array suffices.Benjamin Kramer2017-03-241-75/+70
| | | | | | NFC. llvm-svn: 298701
* Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both ↵Craig Topper2017-03-131-3/+2
| | | | | | | | | | have a memory operand. We should just continue to check other operands instead." This reverts r297596. There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table. llvm-svn: 297602
* [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a ↵Craig Topper2017-03-131-2/+3
| | | | | | | | memory operand. We should just continue to check other operands instead. This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch. llvm-svn: 297596
* [X86] Minor formatting tweaks in EVEX to VEX tables. NFCCraig Topper2017-03-131-45/+45
| | | | llvm-svn: 297595
* [X86] Quick fix for build bot failure (r297127) due to unused variable.Ayman Musa2017-03-071-2/+1
| | | | llvm-svn: 297130
* [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX ↵Ayman Musa2017-03-071-0/+345
compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
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