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* Remove trailing whitespaceCraig Topper2012-07-311-31/+31
| | | | llvm-svn: 161030
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-041-8/+8
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-0/+9
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-2/+0
| | | | llvm-svn: 150918
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-111-1/+1
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. llvm-svn: 150303
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-091-7/+28
| | | | llvm-svn: 150167
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-091-38/+38
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. llvm-svn: 150161
* Remove unreachable code. (replace with llvm_unreachable to help GCC where ↵David Blaikie2012-01-171-1/+0
| | | | | | necessary) llvm-svn: 148284
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-1/+6
| | | | llvm-svn: 143895
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-0/+7
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-071-0/+1
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-15/+13
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Fix typo in r140954.Craig Topper2011-10-021-1/+0
| | | | llvm-svn: 140962
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-011-0/+9
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-1/+5
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP ↵Craig Topper2011-09-111-2/+4
| | | | | | disassembling to ignore OpSize and REX.W. llvm-svn: 139484
* Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form ↵Craig Topper2011-09-021-26/+23
| | | | | | from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. llvm-svn: 138997
* Give ATTR_VEX higher priority when generating the disassembler context ↵Craig Topper2011-08-251-2/+2
| | | | | | table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. llvm-svn: 138552
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-0/+2
| | | | llvm-svn: 128826
* Use array_lengthofJoerg Sonnenberger2011-04-041-2/+3
| | | | llvm-svn: 128823
* Change loops to derive the number of tables automaticallyJoerg Sonnenberger2011-04-041-2/+2
| | | | llvm-svn: 128818
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-3/+58
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Constify another 2 disassembler tables.Benjamin Kramer2010-10-231-2/+3
| | | | llvm-svn: 117208
* Make the disassembler tables const so they end up in read-only memory.Benjamin Kramer2010-10-231-5/+4
| | | | llvm-svn: 117206
* Make some symbols static, move classes into anonymous namespaces.Benjamin Kramer2010-10-221-5/+3
| | | | llvm-svn: 117111
* Fix a bunch of namespace polution.Dan Gohman2010-04-151-2/+2
| | | | llvm-svn: 101376
* Suppress compiler warning.Daniel Dunbar2009-12-231-0/+2
| | | | llvm-svn: 91959
* fix build and while at it remove a redudant includeNuno Lopes2009-12-191-2/+0
| | | | llvm-svn: 91774
* More bzero -> memset that I missed.Daniel Dunbar2009-12-191-1/+1
| | | | llvm-svn: 91757
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-0/+603
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
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