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data.
llvm-svn: 161034
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instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent.
llvm-svn: 161033
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llvm-svn: 161032
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llvm-svn: 161030
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Shaves 150k off the size of X86DisassemblerDecoder.o
llvm-svn: 151995
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Kay Tiong Khoo.
llvm-svn: 151510
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llvm-svn: 150918
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This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.
llvm-svn: 150303
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llvm-svn: 150167
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needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.
llvm-svn: 150161
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necessary)
llvm-svn: 148284
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llvm-svn: 143895
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for 64BIT_REXW_XD not existing, but it does exist.
llvm-svn: 141642
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64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
llvm-svn: 141353
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instructions. Mark instructions that have this behavior. Fixes PR10676.
llvm-svn: 141065
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llvm-svn: 140962
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0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
llvm-svn: 140954
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This is the first step towards splitting LLVM and Clang's tblgen executables.
llvm-svn: 140951
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Fixes part of PR10700.
llvm-svn: 140370
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disassembling to ignore OpSize and REX.W.
llvm-svn: 139484
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from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
llvm-svn: 138997
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table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
llvm-svn: 138552
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llvm-svn: 128826
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llvm-svn: 128823
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llvm-svn: 128818
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instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644
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llvm-svn: 117208
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llvm-svn: 117206
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llvm-svn: 117111
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llvm-svn: 101376
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llvm-svn: 91959
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llvm-svn: 91774
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llvm-svn: 91757
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incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
llvm-svn: 91749
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