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* [TableGen] Add a general-purpose JSON backend.Simon Tatham2018-07-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aim of this backend is to output everything TableGen knows about the record set, similarly to the default -print-records backend. But where -print-records produces output in TableGen's input syntax (convenient for humans to read), this backend produces it as structured JSON data, which is convenient for loading into standard scripting languages such as Python, in order to extract information from the data set in an automated way. The output data contains a JSON representation of the variable definitions in output 'def' records, and a few pieces of metadata such as which of those definitions are tagged with the 'field' prefix and which defs are derived from which classes. It doesn't dump out absolutely every piece of knowledge it _could_ produce, such as type information and complicated arithmetic operator nodes in abstract superclasses; the main aim is to allow consumers of this JSON dump to essentially act as new backends, and backends don't generally need to depend on that kind of data. The new backend is implemented as an EmitJSON() function similar to all of llvm-tblgen's other EmitFoo functions, except that it lives in lib/TableGen instead of utils/TableGen on the basis that I'm expecting to add it to clang-tblgen too in a future patch. To test it, I've written a Python script that loads the JSON output and tests properties of it based on comments in the .td source - more or less like FileCheck, except that the CHECK: lines have Python expressions after them instead of textual pattern matches. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arichardson, labath, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46054 llvm-svn: 336771
* [IR] Split Intrinsics.inc into enums and implementationsReid Kleckner2018-06-231-8/+20
| | | | | | | | | | | | | | | | | | | Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
* Remove redundant includes from utils/TableGen.Michael Zolotukhin2017-12-131-1/+0
| | | | llvm-svn: 320632
* [Docs] Add tablegen backend for target opcode documentationOliver Stannard2017-11-141-0/+6
| | | | | | | | | | This is a tablegen backend to generate documentation for the opcodes that exist for each target. For each opcode, it lists the assembly string, the names and types of all operands, and the flags and predicates that apply to the opcode. Differential revision: https://reviews.llvm.org/D31025 llvm-svn: 318155
* [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend ↵Ayman Musa2017-10-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | while disabling it by default. After the original commit ([[ https://reviews.llvm.org/rL304088 | rL304088 ]]) was reverted, a discussion in llvm-dev was opened on 'how to accomplish this task'. In the discussion we concluded that the best way to achieve our goal (which is to automate the folding tables and remove the manually maintained tables) is: # Commit the tablegen backend disabled by default. # Proceed with an incremental updating of the manual tables - while checking the validity of each added entry. # Repeat previous step until we reach a state where the generated and the manual tables are identical. Then we can safely remove the manual tables and include the generated tables instead. # Schedule periodical (1 week/2 weeks/1 month) runs of the pass: - if changes appear (new entries): - make sure the entries are legal - If they are not, mark them as illegal to folding - Commit the changes (if there are any). CMake flag added for this purpose is "X86_GEN_FOLD_TABLES". Building with this flags will run the pass and emit the X86GenFoldTables.inc file under build/lib/Target/X86/ directory which is a good reference for any developer who wants to take part in the effort of completing the current folding tables. Differential Revision: https://reviews.llvm.org/D38028 llvm-svn: 315173
* [TableGen] Ensure that __lsan_is_turned_off isn't removed by DCE in llvm-tblgenFrancis Ricci2017-09-111-1/+1
| | | | | | | | | | | | | | Summary: Since asan is linked dynamically on Darwin, the weak interface symbol is removed by -Wl,-dead_strip. Reviewers: kcc, compnerd, aaron.ballman Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37636 llvm-svn: 312914
* [x86] Revert the X86FoldTablesEmitter due to more miscompiles.Chandler Carruth2017-06-061-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In testing, we've found yet another miscompile caused by the new tables. And this one is even less clear how to fix (we could teach it to fold a 16-bit load instead of the 32-bit load it wants, or block folding entirely). Also, the approach to excluding instructions seems increasingly to not scale well. I have left a more detailed analysis on the review log for the original patch (https://reviews.llvm.org/D32684) along with suggested path forward. I will land an additional test case that I wrote which covers the code that was miscompiling (folding into the output of `pextrw`) in a subsequent commit to keep this a pure revert. For each commit reverted here, I've restricted the revert to the non-test code touching the x86 fold table emission until the last commit where I did revert the test updates. This means the *new* test cases added for `insertps` and `xchg` remain untouched (and continue to pass). Reverted commits: r304540: [X86] Don't fold into memory operands into insertps in the ... r304347: [TableGen] Adapt more places to getValueAsString now ... r304163: [X86] Don't fold away the memory operand of an xchg. r304123: Don't capture a temporary std::string in a StringRef. r304122: Resubmit "[X86] Adding new LLVM TableGen backend that ..." Original commit was in r304088, and after a string of fixes was reverted previously in r304121 to fix build bots, and then re-landed in r304122. llvm-svn: 304762
* Resubmit "[X86] Adding new LLVM TableGen backend that generates the X86 ↵Zachary Turner2017-05-291-0/+6
| | | | | | | | | | | | | backend memory folding tables." This was reverted due to buildbot breakages and I was not familiar with this code to investigate it. But while trying to get a useful backtrace for the author, it turns out the fix was very obvious. Resubmitting this patch as is, and will submit the fix in a followup so that the fix is not hidden in the larger CL. llvm-svn: 304122
* Revert "[X86] Adding new LLVM TableGen backend that generates the X86 ↵Zachary Turner2017-05-291-6/+0
| | | | | | | | | | | | | backend memory folding tables." This reverts commit 28cb1003507f287726f43c771024a1dc102c45fe as well as all subsequent followups. llvm-tblgen currently segfaults with this change, and it seems it has been broken on the bots all day with no fixes in preparation. See, for example: http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/ llvm-svn: 304121
* [X86] Adding new LLVM TableGen backend that generates the X86 backend memory ↵Ayman Musa2017-05-281-0/+6
| | | | | | | | | | | folding tables. X86 backend holds huge tables in order to map between the register and memory forms of each instruction. This TableGen Backend automatically generated all these tables with the appropriate flags for each entry. Differential Revision: https://reviews.llvm.org/D32684 llvm-svn: 304088
* [tablegen] Use categories on options that only matter to one emitter.Daniel Sanders2017-03-271-1/+2
| | | | | | | | | | | | | | | | Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
* [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX ↵Ayman Musa2017-03-071-0/+6
| | | | | | | | | | | | compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
* [globalisel] Fix missing break.Daniel Sanders2017-02-031-0/+1
| | | | | | The instruction selector has been emitting the register bank information too. llvm-svn: 294007
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-191-1/+6
| | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
* Re-revert: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-181-6/+1
| | | | | | | More missing guards. My build didn't notice it due to a stale file left over from a Global ISel build. llvm-svn: 292369
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-181-1/+6
| | | | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since last commit: The new tablegen pass is now correctly guarded by LLVM_BUILD_GLOBAL_ISEL and this should fix the buildbots however it may not be the whole fix. The previous buildbot failures suggest there may be a memory bug lurking that I'm unable to reproduce (including when using asan) or spot in the source. If they re-occur on this commit then I'll need assistance from the bot owners to track it down. Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292367
* Revert r292132: [globalisel] Tablegen-erate current Register Bank ↵Daniel Sanders2017-01-161-6/+1
| | | | | | | | | Information'... Several buildbots encountered a crash in tablegen when building this commit. Reverting while I investigate the cause. llvm-svn: 292136
* [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-161-1/+6
| | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292132
* [GlobalISel] Add basic Selector-emitter tblgen backend.Ahmed Bougacha2016-12-211-1/+7
| | | | | | | | | | | | | | | | | This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-081-2/+1
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* AArch64: TableGenerate system instruction operands.Tim Northover2016-07-051-1/+7
| | | | | | | | | | | | | | | | | | | | The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
* Search for llvm-symbolizer binary in the same directory as argv[0], beforeRichard Smith2016-06-091-1/+1
| | | | | | | looking for it along $PATH. This allows installs of LLVM tools outside of $PATH to find the symbolizer and produce pretty backtraces if they crash. llvm-svn: 272232
* [TableGen] Call llvm_shutdown on exit so that all the ManagedStatic objects ↵Craig Topper2016-01-041-0/+3
| | | | | | in the support library will be deleted. llvm-svn: 256732
* Move the enum attributes defined in Attributes.h to a table-gen file.Akira Hatanaka2015-11-111-1/+7
| | | | | | | | | | | | | | This is a step towards consolidating some of the information regarding attributes in a single place. This patch moves the enum attributes in Attributes.h to the table-gen file. Additionally, it adds definitions of target independent string attributes that will be used in follow-up commits by the inliner to check attribute compatibility. rdar://problem/19836465 llvm-svn: 252796
* Use range-based for loops. NFCCraig Topper2014-12-111-9/+7
| | | | llvm-svn: 224005
* Move SetTheory from utils/TableGen into lib/TableGen so Clang can use it.James Molloy2014-06-171-1/+1
| | | | llvm-svn: 211100
* replace LeakSanitizerIsTurnedOffForTheCurrentProcess with ↵Kostya Serebryany2014-01-151-5/+7
| | | | | | __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h> llvm-svn: 199303
* reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; ↵Kostya Serebryany2014-01-101-0/+7
| | | | | | this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off llvm-svn: 198922
* Revert "Disable LeakSanitizer in TableGen binaries, see PR18325"Alp Toker2014-01-091-7/+0
| | | | | | | | | | | To declare or define reserved identifers is undefined behaviour in standard C++. This needs to be addressed in compiler-rt before it can be used in LLVM. See the list discussion for details. This reverts commit r198858. llvm-svn: 198884
* Disable LeakSanitizer in TableGen binaries, see PR18325Kostya Serebryany2014-01-091-0/+7
| | | | llvm-svn: 198858
* Add TableGen ctags(1) emitter and helper script.Sean Silva2013-03-211-1/+7
| | | | | | | | | | | | | | | | | | | | | To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) llvm-svn: 177682
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-6/+0
| | | | llvm-svn: 170578
* Copy clang/Driver/<Option parsing stuff> to llvm.Michael J. Spencer2012-12-051-1/+7
| | | | llvm-svn: 169344
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-1/+0
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* tblgen: Migrate llvm-tblgen to new TableGenMain API.Sean Silva2012-10-031-82/+77
| | | | llvm-svn: 165166
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-32/+19
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Removing unused default switch cases in switches over enums that already ↵David Blaikie2012-01-161-3/+0
| | | | | | | | account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
* Unweaken vtables as per ↵David Blaikie2011-12-201-84/+84
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Add a deterministic finite automaton based packetizer for VLIW architecturesAnshuman Dasgupta2011-12-011-0/+7
| | | | llvm-svn: 145629
* Remove the old-style ARM disassembler, which is no longer used.Owen Anderson2011-11-091-7/+0
| | | | llvm-svn: 144243
* Remove the Clang tblgen backends from LLVM.Peter Collingbourne2011-10-061-122/+0
| | | | llvm-svn: 141293
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-144/+61
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Remove more of llvmc and dependencies.Eric Christopher2011-09-201-7/+0
| | | | llvm-svn: 140121
* Added LateParsed property to TableGen attributes.Caitlin Sadowski2011-09-081-0/+7
| | | | | | This patch was written by DeLesley Hutchins. llvm-svn: 139300
* Dependency should be on the output file name, not the dependency fileJoerg Sonnenberger2011-09-071-1/+1
| | | | | | name. llvm-svn: 139220
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-12/+1
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-1/+12
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* TableGen'erated MC lowering for simple pseudo-instructions.Jim Grosbach2011-07-081-0/+7
| | | | | | | | | | | | This allows the (many) pseudo-instructions we have that map onto a single real instruction to have their expansion during MC lowering handled automatically instead of the current cumbersome manual expansion required. These sorts of pseudos are common when an instruction is used in situations that require different MachineInstr flags (isTerminator, isBranch, et. al.) than the generic instruction description has. For example, using a move to the PC to implement a branch. llvm-svn: 134704
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-9/+5
| | | | llvm-svn: 134024
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