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path: root/llvm/utils/TableGen/SubtargetEmitter.cpp
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* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-36/+52
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-52/+36
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* Replace size method call of containers to empty method where appropriateAlexander Kornienko2015-01-151-1/+1
| | | | | | | | | | | | | | | | This patch was generated by a clang tidy checker that is being open sourced. The documentation of that checker is the following: /// The emptiness of a container should be checked using the empty method /// instead of the size method. It is not guaranteed that size is a /// constant-time function, and it is generally more efficient and also shows /// clearer intent to use empty. Furthermore some containers may implement the /// empty method but not implement the size method. Using empty whenever /// possible makes it easier to switch to another container in the future. Patch by Gábor Horváth! llvm-svn: 226161
* Update SetVector to rely on the underlying set's insert to return a ↵David Blaikie2014-11-191-2/+2
| | | | | | | | | | | | | pair<iterator, bool> This is to be consistent with StringSet and ultimately with the standard library's associative container insert function. This lead to updating SmallSet::insert to return pair<iterator, bool>, and then to update SmallPtrSet::insert to return pair<iterator, bool>, and then to update all the existing users of those functions... llvm-svn: 222334
* Tablegen scheduling models don't reference empty itineraries as of r216919, ↵Pete Cooper2014-09-021-4/+5
| | | | | | so don't emit the unused itinerary variables llvm-svn: 216993
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-021-4/+4
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-0/+4
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* Move late partial-unrolling thresholds into the processor definitionsHal Finkel2014-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. llvm-svn: 208289
* Debug.h already includes raw_ostream.h, no need to include it again.Eric Christopher2014-05-071-1/+0
| | | | llvm-svn: 208235
* ArrayRef-ize the Feature and Processor tables for SubtargetFeatures.Eric Christopher2014-05-061-12/+12
| | | | | | | | This removes arguments passed everywhere and allows the use of standard iteration over lists. Should be no functional change. llvm-svn: 208127
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-301-1/+1
| | | | llvm-svn: 207611
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-6/+6
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-1/+1
| | | | | | class. llvm-svn: 203378
* Mark the x86 machine model as incomplete. PR17367.Andrew Trick2013-09-251-0/+5
| | | | | | | | | | | | Ideally, the machinel model is added at the time the instructions are defined. But many instructions in X86InstrSSE.td still need a model. Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too. llvm-svn: 191391
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-151-5/+1
| | | | | | And add Sandybridge/Haswell resource buffers. llvm-svn: 184034
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-10/+7
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* SubtargetEmitter fixArnold Schwaighofer2013-06-051-1/+1
| | | | | | | | | Don't output data if we are supposed to ignore the record. Reapply of 183255, I don't think this was causing the tablegen segfault on linux testers. llvm-svn: 183311
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-1/+1
| | | | llvm-svn: 183273
* SubtargetEmitter fixArnold Schwaighofer2013-06-041-1/+1
| | | | | | Don't output data if we are supposed to ignore the record. llvm-svn: 183255
* Machine model: Generate table entries for super-resources.Andrew Trick2013-04-231-14/+23
| | | | | | | | | Super-resources and resource groups are two ways of expressing overlapping sets of processor resources. Now we generate table entries the same way for both so the scheduler never needs to explicitly check for super-resources. llvm-svn: 180162
* Machine model: rewrite a tablegen loop to avoid comparing record pointers.Andrew Trick2013-04-231-8/+4
| | | | llvm-svn: 180160
* TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2013-03-261-1/+16
| | | | | | Allow variants to be defined only for some processors on a target. llvm-svn: 178074
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-161-43/+35
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
* Fix r177112: Add ProcResGroup.Andrew Trick2013-03-141-1/+3
| | | | | | This is the other half of r177122 that I meant to commit at the same time. llvm-svn: 177123
* MachineModel: Add a ProcResGroup class.Andrew Trick2013-03-141-12/+75
| | | | | | | | | | | | | | | | | This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; llvm-svn: 177112
* MIsched machine model: tablegen subtarget emitter improvement.Andrew Trick2013-03-011-1/+14
| | | | | | | | Fix the way resources are counted. I'm taking some time to cleanup the way MachineScheduler handles in-order machine resources. Eventually we'll need more PPC/Atom test cases in tree. llvm-svn: 176390
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-0/+1
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-3/+3
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Fix a build problem with xlc. The error message wasRafael Espindola2012-11-021-1/+1
| | | | | | | | | "../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+". "../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate. Patch by Kai. llvm-svn: 167311
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-7/+7
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* misched: Generate IsBuffered flag for machine resources.Andrew Trick2012-10-101-4/+4
| | | | llvm-svn: 165602
* TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick2012-10-031-8/+14
| | | | | | | | | A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. llvm-svn: 165179
* Cleanup TableGen subtarget emitter.Andrew Trick2012-10-031-2/+6
| | | | llvm-svn: 165178
* Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick2012-09-221-22/+82
| | | | | | | Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. llvm-svn: 164451
* SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick2012-09-191-7/+26
| | | | llvm-svn: 164199
* Replaced ReInitMCSubtargetInfo with InitMCProcessor.Andrew Trick2012-09-181-1/+2
| | | | | | | | Now where we used to call ReInitMCSubtargetInfo, we actually recompute the same information as InitMCSubtargetInfo instead of only setting the feature bits. llvm-svn: 164105
* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-181-0/+84
| | | | | | resolving instruction variants. llvm-svn: 164095
* TableGen subtarget emitter. Remove unnecessary header dependence.Andrew Trick2012-09-181-0/+1
| | | | llvm-svn: 164094
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-6/+25
| | | | | | model. llvm-svn: 164092
* Backout the wrong subtarget emitter fixAndrew Trick2012-09-171-1/+1
| | | | llvm-svn: 164078
* Fix release build after revertingAndrew Trick2012-09-171-2/+1
| | | | llvm-svn: 164075
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-111/+8
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* InitMCProcessorAndrew Trick2012-09-171-1/+2
| | | | llvm-svn: 164066
* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-171-0/+84
| | | | | | resolving instruction variants. llvm-svn: 164062
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-7/+25
| | | | | | model. llvm-svn: 164061
* TableGen subtarget emitter. Format and emit data tables for the new machine ↵Andrew Trick2012-09-171-6/+117
| | | | | | model. llvm-svn: 164060
* TableGen subtarget emitter. Generate data tables for the new machine model.Andrew Trick2012-09-171-2/+291
| | | | | | | | | | | | Map the CodeGenSchedule object model onto data tables. The structure of the data tables is defined in MC, so for convenience we include MCSchedule.h. The alternative is maintaining a redundant copy of the table structure definitions. Mapping the object model onto data tables is sufficiently complicated that it should not be interleaved with emitting source code. This avoids major problem with the backend for itinerary generation. llvm-svn: 164059
* TableGen subtarget emitter. Emit processor resources for the new machine model.Andrew Trick2012-09-171-10/+63
| | | | llvm-svn: 164058
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-151-3/+3
| | | | | | Collect SchedClasses and SchedRW types from the subtarget defs. llvm-svn: 163951
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