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* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-311-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* [Tablegen] Avoid generating empty switch statements. NFCAndrea Di Biagio2018-05-271-4/+10
| | | | | | | This fixes an MSVC warning (warning C4065: switch statement contains 'default' but no 'case' labels) introduced with revision 333293. llvm-svn: 333363
* [Tablegen][SubtargetEmitter] Add a default case to the auto-generated switch ↵Andrea Di Biagio2018-05-251-1/+3
| | | | | | in MCSubtargetInfo::resolveVariantSchedClass(). NFC llvm-svn: 333293
* [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling ↵Andrea Di Biagio2018-05-251-1/+24
| | | | | | | | | | | | | | | | | | | | classes. This patch is the second of a sequence of three patches related to LLVM-dev RFC "MC support for varinat scheduling classes". https://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to enable the resolution of variant classes in MC with the help of a new method named `MCSubtargetInfo::resolveVariantSchedClass()`. This patch also teaches the SubtargetEmitter how to automatically generate the definition of method resolveVariantSchedClass(). That definition is emitted within a sub-class of MCSubtargetInfo named XXXGenMCSubtargetInfo (where XXX is the name of the Target). Differential Revision: https://reviews.llvm.org/D47077 llvm-svn: 333286
* [RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.Andrea Di Biagio2018-05-251-30/+76
| | | | | | | | | | | | | | | | | | | | | | This patch is the first of a sequence of three patches described by the LLVM-dev RFC "MC support for variant scheduling classes". http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to introduce a new class of scheduling predicates for SchedReadVariant and SchedWriteVariant. An MCSchedPredicate can be used instead of a normal SchedPredicate to model checks on the instruction (either a MachineInstr or a MCInst). Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition. MCInstPredicate allows the definition of expressions with a well-known semantic, that can be used to generate code for both MachineInstr and MCInst. This is the first step toward teaching to tools like lllvm-mca how to resolve variant scheduling classes. Differential Revision: https://reviews.llvm.org/D46695 llvm-svn: 333282
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-6/+7
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [Tablegen] SubtargetEmitter: move the logic that prints predicates for ↵Andrea Di Biagio2018-04-261-21/+47
| | | | | | variant scheduling classes to helper functions. NFC llvm-svn: 330968
* [llvm-exegesis] Fix PfmIssueCountersTable creationSimon Pilgrim2018-04-191-6/+11
| | | | | | | | | | | | | | This patch ensures that the pfm issue counter tables are the correct size, accounting for the invalid resource entry at the beginning of the resource tables. It also fixes an issue with pfm failing to match event counters due to a trailing comma added to all the event names. I've also added a counter comment to each entry as it helps locate problems with the tables. Note: I don't have access to a SandyBridge test machine, which is the only model to make use of multiple event counters being mapped to a single resource. I don't know if pfm accepts a comma-seperated list or not, but that is what it was doing. Differential Revision: https://reviews.llvm.org/D45787 llvm-svn: 330317
* [MC][TableGen] Fix r329675.Clement Courbet2018-04-101-4/+6
| | | | | | Caught by bots with -Wmissing-braces. llvm-svn: 329676
* [MC][TableGen] Add optional libpfm counter names for ProcResUnits.Clement Courbet2018-04-101-3/+59
| | | | | | | | | | | | | | | | Summary: Subtargets can define the libpfm counter names that can be used to measure cycles and uops issued on ProcResUnits. This allows making llvm-exegesis available on more targets. Fixes PR36984. Reviewers: gchatelet, RKSimon, andreadb, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45360 llvm-svn: 329675
* [TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-061-9/+9
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
* Fix the buildbots after r329304.Andrea Di Biagio2018-04-051-1/+1
| | | | llvm-svn: 329306
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-051-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [MC] Fix spaces between values printed by EmitRegisterFileInfo.Andrea Di Biagio2018-04-051-2/+2
| | | | llvm-svn: 329284
* [Tablegen] Slightly refactor method SubtargetEmitter::EmitExtraProcessorInfo.Andrea Di Biagio2018-04-041-10/+41
| | | | | | | This patch moves most of the logic from EmitExtraProcessorInfo to a couple of helper functions. No functional change intended. llvm-svn: 329173
* [MC][Tablegen] Allow the definition of processor register files in the ↵Andrea Di Biagio2018-04-031-2/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scheduling model for llvm-mca This patch allows the description of register files in processor scheduling models. This addresses PR36662. A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td. Targets can optionally describe register files for their processors using that class. In particular, class RegisterFile allows to specify: - The total number of physical registers. - Which target registers are accessible through the register file. - The cost of allocating a register at register renaming stage. Example (from this patch - see file X86/X86ScheduleBtVer2.td) def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]> Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar (btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM register definitions only cost 1 physical register. The syntax allows to specify an empty set of register classes. An empty set of register classes means: this register file models all the registers specified by the Target. For each register class, users can specify an optional register cost. By default, register costs default to 1. A value of 0 for the number of physical registers means: "this register file has an unbounded number of physical registers". This patch is structured in two parts. * Part 1 - MC/Tablegen * A first part adds the tablegen definition of RegisterFile, and teaches the SubtargetEmitter how to emit information related to register files. Information about register files is accessible through an instance of MCExtraProcessorInfo. The idea behind this design is to logically partition the processor description which is only used by external tools (like llvm-mca) from the processor information used by the llvm machine schedulers. I think that this design would make easier for targets to get rid of the extra processor information if they don't want it. * Part 2 - llvm-mca related * The second part of this patch is related to changes to llvm-mca. The main differences are: 1) class RegisterFile now needs to take into account the "cost of a register" when allocating physical registers at register renaming stage. 2) Point 1. triggered a minor refactoring which lef to the removal of the "maximum 32 register files" restriction. 3) The BackendStatistics view has been updated so that we can print out extra details related to each register file implemented by the processor. The effect of point 3. is also visible in tests register-files-[1..5].s. Differential Revision: https://reviews.llvm.org/D44980 llvm-svn: 329067
* [TableGen] Don't capture returned std::vectors by const reference.Craig Topper2018-03-231-12/+8
| | | | | | The full vector is being returned not a reference. So the reference was just a to a temporary. llvm-svn: 328275
* Fix some user facing typosSylvestre Ledru2018-03-171-2/+2
| | | | llvm-svn: 327776
* [MCSchedule] Always generate processor resource names.Andrea Di Biagio2018-03-081-2/+2
| | | | | | | | | | | | With this patch, the tablegen 'SubtargetEmitter' always generates processor resource names. The impact of this patch on the code size of other llvm tools is small. I have observed an average increase of 0.03% in code size when doing a release build of LLVM (on windows, using MSVC) with all the default backends. This change is done in preparation for the upcoming llvm-mca patch. llvm-svn: 326993
* Shrink various scheduling tables by using narrower types.Benjamin Kramer2018-02-231-7/+12
| | | | | | 16 bits ought to be enough for everyone. This shrinks clang by ~1MB. llvm-svn: 325941
* [TargetSchedule] Fix r324582.Clement Courbet2018-02-091-1/+1
| | | | | | | Increment was using the wrong NumUnits (the one from the ProcResGroup and not the subunit). llvm-svn: 324727
* Fix missing field initializer warning in TableGen SubtargetEmitterDavid Blaikie2018-02-081-3/+4
| | | | llvm-svn: 324643
* [TargetSchedule] Expose sub-units of a ProcResGroup in MCProcResourceDesc.Clement Courbet2018-02-081-3/+39
| | | | | | | | | | | | | | | | | | Summary: Right now using a ProcResource automatically counts as usage of all super ProcResGroups. All this is done during codegen, so there is no way for schedulers to get this information at runtime. This adds the information of which individual ProcRes units are contained in a ProcResGroup in MCProcResourceDesc. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43023 llvm-svn: 324582
* [TableGen] Improve error reportingEvandro Menezes2017-11-211-4/+6
| | | | | | | | | When searching for a resource unit, use the reference location instead of the definition location in case of an error. Differential revision: https://reviews.llvm.org/D40263 llvm-svn: 318803
* [TableGen] Use Twine instead of std::string concatenation in two calls to ↵Craig Topper2017-10-261-4/+4
| | | | | | PrintFatalError. llvm-svn: 316697
* [TableGen] Fix some formatting quirks in the subtarget output file.Craig Topper2017-10-241-4/+5
| | | | llvm-svn: 316450
* [TableGen] Simplify some of the subtarget emission by removing code that ↵Craig Topper2017-10-241-45/+11
| | | | | | | | avoids printing commas at the end of arrays and enums. The C++ standard allows for trailing commas. We already do this in many other emitters. llvm-svn: 316449
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-151-1/+1
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-1/+1
| | | | | | | | | | | | | | | Summary: Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP. Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods. Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so it'll be picked up by public headers. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 315590
* [TableGen] Simplify SubtargetEmitterJaved Absar2017-10-061-8/+4
| | | | | | Remove unnecessary duplicate if-condition. llvm-svn: 315068
* Cleanup some problems with LLVM_ENABLE_DUMP in release builds, andDon Hinton2017-09-271-1/+1
| | | | | | | | always set LLVM_ENABLE_DUMP=ON for +Asserts builds. Differential Revision: https://reviews.llvm.org/D38306 llvm-svn: 314346
* Subtarget support for parameterized register class informationKrzysztof Parzyszek2017-09-141-5/+27
| | | | | | | | Implement "checkFeatures" and emitting HW mode check code. Differential Revision: https://reviews.llvm.org/D31959 llvm-svn: 313295
* [tablegen] Avoid creating temporary stringsAlexander Shaposhnikov2017-07-051-6/+3
| | | | | | | | | | | | | If a method / function returns a StringRef but the variable is of type const std::string& a temporary string is created (StringRef has a cast operator to std::string), which is a suboptimal behavior. Differential revision: https://reviews.llvm.org/D34994 Test plan: make check-all llvm-svn: 307195
* [TableGen] Improve Debug Output for --debug-only=subtarget-emitter NFCIJoel Jones2017-06-281-0/+1
| | | | | | | | | Add headers for each section of output, with white space and "+++" to improve readability. Differential Revision: https://reviews.llvm.org/D34713 llvm-svn: 306492
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-311-8/+8
| | | | | | instead of a std::string. llvm-svn: 304347
* Fix comment typos.Geoff Berry2017-05-081-1/+1
| | | | llvm-svn: 302432
* Improve machine schedulers for in-order processorsJaved Absar2017-03-271-0/+2
| | | | | | | | | | | This patch enables schedulers to specify instructions that cannot be issued with any other instructions. It also fixes BeginGroup/EndGroup. Reviewed by: Andrew Trick Differential Revision: https://reviews.llvm.org/D30744 llvm-svn: 298885
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-091-13/+14
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289282
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-2/+2
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Use StringRef in TableGen (NFC)Mehdi Amini2016-10-041-2/+2
| | | | llvm-svn: 283273
* Use the range variant of find/find_if instead of unpacking begin/endDavid Majnemer2016-08-121-6/+2
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278469
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-4/+2
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* Apply most suggestions of clang-tidy's performance-unnecessary-value-paramBenjamin Kramer2016-06-081-2/+2
| | | | | | | Avoids unnecessary copies. All changes audited & pass tests with asan. No functional change intended. llvm-svn: 272190
* Fix Clang-tidy modernize-use-bool-literals in generated Target code; other ↵Eugene Zelenko2016-05-171-25/+37
| | | | | | | | | | | | minor fixes; other minor fixes. Make generated code more readable. Fix some Include What You Use warnings. Differential revision: http://reviews.llvm.org/D20317 llvm-svn: 269783
* [TableGen] Remove constant string argument from a method that's only called ↵Craig Topper2016-02-141-5/+5
| | | | | | once. We can just hardcode the string inside. There already other things that make the method not reusable. NFC llvm-svn: 260840
* [TableGen] Fix comment about 64-bit type I missed when I removed the ↵Craig Topper2016-02-131-1/+1
| | | | | | underlying type in r260808. llvm-svn: 260830
* [TableGen] Use range-based for loops. NFCCraig Topper2016-02-131-131/+104
| | | | llvm-svn: 260809
* No need to make the subtarget feature bit enum a uint64_t. This was a ↵Craig Topper2016-02-131-1/+1
| | | | | | leftover from when the feature bit enum contained masks instead of bit indices. llvm-svn: 260808
* [TableGen] Simplify some code slightly. No need to check if the arrays are ↵Craig Topper2016-01-031-18/+10
| | | | | | empty before printing. The loop can be made to print the same thing if the loop is empty. NFC llvm-svn: 256703
* Fix Clang-tidy modernize-use-nullptr warnings in source directories and ↵Hans Wennborg2015-10-061-8/+9
| | | | | | | | | | generated files; other minor cleanups. Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D13321 llvm-svn: 249482
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