summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Introduce the DwarfRegAlias class for declaring that two registers have theRafael Espindola2011-05-301-0/+11
| | | | | | | | | | same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. llvm-svn: 132314
* Fix the root cause of the bootstrap failure:Rafael Espindola2011-05-281-7/+2
| | | | | | | | There was no way to check if a given register/mode pair was valid. We now return an error code (-2) instead of asserting. If anyone thinks that an assert at this point is really needed, we can autogen a hasValidDwarfRegNum instead. llvm-svn: 132236
* Downgrade a tablegen warning to an error.Jakob Stoklund Olesen2011-05-101-3/+2
| | | | | | | Ambiguous sub-register index compositions are OK as long as the backend writer knows what he is doing. llvm-svn: 131134
* Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen2011-05-071-19/+34
| | | | | | | The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. llvm-svn: 131058
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-201-3/+4
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-111-1/+4
| | | | llvm-svn: 127448
* Trailing whitespace.Jim Grosbach2011-03-111-45/+45
| | | | llvm-svn: 127446
* Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of allJakob Stoklund Olesen2010-12-141-13/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | registers that alias Reg, including itself. This is almost the same as the existing getAliasSet() method, except for the inclusion of Reg. The name matches the reflexive TRI::regsOverlap(x, y) relation. It is very common to do stuff to a register and all its aliases: stuff(Reg) for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) stuff(*Alias); That can now be written as the simpler: for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) stuff(*Alias); This change requires a bit more constant space for the alias lists because Reg is included and because the empty alias list cannot be shared any longer. If the getAliasSet method is eventually removed, this space can be reclaimed by sharing overlap lists. For instance, %rax and %eax have identical overlap sets. llvm-svn: 121800
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-3/+3
| | | | llvm-svn: 121659
* Split out register class subclassing to a separate function and clean upEric Christopher2010-08-251-29/+1
| | | | | | accordingly. No functional change. llvm-svn: 112008
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-1/+1
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Emit TargetRegisterInfo::composeSubRegIndices().Jakob Stoklund Olesen2010-05-281-18/+114
| | | | | | Also verify that all subregister indices compose unambiguously. llvm-svn: 105064
* Check that inherited subregisters all have a direct SubRegIndex.Jakob Stoklund Olesen2010-05-261-2/+25
| | | | llvm-svn: 104755
* Suppress emmission of empty subreg/superreg/alias sets.Jakob Stoklund Olesen2010-05-261-3/+9
| | | | llvm-svn: 104741
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-36/+83
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-83/+36
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-36/+83
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-251-84/+5
| | | | llvm-svn: 104650
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-251-1/+12
| | | | llvm-svn: 104628
* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-251-2/+1
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. llvm-svn: 104615
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-6/+9
| | | | llvm-svn: 104571
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-66/+69
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-241-4/+21
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. llvm-svn: 104492
* Remove unneeded ';' and a class/struct mismatch (noticed by clang).Daniel Dunbar2009-12-091-1/+1
| | | | llvm-svn: 90934
* Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to ↵Evan Cheng2009-11-141-0/+18
| | | | | | replace broken code in VirtRegRewriter. llvm-svn: 88753
* eliminate the TargetRegisterDesc::AsmName field, the asmprinters now have ↵Chris Lattner2009-09-131-6/+1
| | | | | | this table. llvm-svn: 81728
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-1/+1
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-2/+2
| | | | | | own struct type. llvm-svn: 78610
* Minor whitespace tidiness.Dan Gohman2009-07-301-4/+4
| | | | llvm-svn: 77564
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-24/+23
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Slightly change TableGen's definition of a register subclass.Jakob Stoklund Olesen2009-04-301-1/+14
| | | | | | | | | | | | | | | | | | | | | | | A subclass is allowed to have a larger spill size than the superclass, and the spill alignment must be a multiple of the superclass alignment. This causes the following new subclass relations: === Alpha === F4RC -> F8RC === PPC === F4RC -> F8RC === SPU === R8C -> R16C -> R32C/R32FP -> R64C/R64FP -> GPRC/VECREG === X86 === FR32 -> FR64 -> VR128 RFP32 -> RFP64 -> RFP80 These subclass relations are consistent with the behaviour of -join-cross-class-copies. llvm-svn: 70511
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-0/+79
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Give register alias checking the hash table treatment too.Owen Anderson2009-04-091-1/+78
| | | | llvm-svn: 68730
* Convert TargetRegisterInfo's super-register checking to use a pre-computed ↵Owen Anderson2009-04-091-1/+79
| | | | | | hash table just like subregister checking does. llvm-svn: 68669
* "This adds a getName() method to TargetRegisterClass, just like in ↵Chris Lattner2009-04-031-0/+1
| | | | | | | | | | TargetRegisterInfo. This makes debugging register classes a bit easier." Patch by Jakob Stoklund Olesen! llvm-svn: 68400
* Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and ↵Evan Cheng2009-01-221-78/+0
| | | | | | SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. llvm-svn: 62762
* Fun x86 encoding tricks: when adding an immediate value of 128,Dan Gohman2008-10-171-2/+2
| | | | | | | | | | | | | use a SUB instruction instead of an ADD, because -128 can be encoded in an 8-bit signed immediate field, while +128 can't be. This avoids the need for a 32-bit immediate field in this case. A similar optimization applies to 64-bit adds with 0x80000000, with the 32-bit signed immediate field. To support this, teach tablegen how to handle 64-bit constants. llvm-svn: 57663
* Indentation.Evan Cheng2008-09-111-2/+2
| | | | llvm-svn: 56107
* Change getSubReg semantics. It now returns zero if the specified register ↵Evan Cheng2008-09-111-2/+2
| | | | | | doesn't have a subreg of the specified index. llvm-svn: 56099
* Fix typos in (generated) comments.Dan Gohman2008-09-081-2/+2
| | | | llvm-svn: 55916
* - small bug corrected: incorrect iterator type.Cedric Venet2008-08-261-2/+2
| | | | | | - fix to please VS: add a return after an assert. llvm-svn: 55380
* stabilize more printing, this doesn't cause a problemChris Lattner2008-08-261-10/+8
| | | | | | in the example attached to PR2590, but is a problem in general. llvm-svn: 55361
* stablize SubRegsSet printing, part of PR2590Chris Lattner2008-08-261-6/+8
| | | | llvm-svn: 55360
* Stabilize 'getDwarfRegNumFull' output to not depend on random memory Chris Lattner2008-08-261-4/+8
| | | | | | orders, part of PR2590 llvm-svn: 55359
* Speed up addRegisterDead by adding more fast checks before performing the ↵Owen Anderson2008-08-141-3/+9
| | | | | | | | | expensive subregister query, and by increasing the size of the subregister hashtable so that there are fewer collisions. llvm-svn: 54781
* TargetRegisterDesc::Name field is the same as the abstract register name. ↵Evan Cheng2008-07-071-10/+1
| | | | | | There is no need for targets to specify register names in addition to their AsmName's. llvm-svn: 53207
* Make the subregister hashtable output more readable by wrapping the lines,Owen Anderson2008-07-011-12/+16
| | | | | | and mark it const along with the associated changes to TargetRegisterInfo. llvm-svn: 52966
* Use delete[] instead of free on an array created with new[].Owen Anderson2008-07-011-1/+1
| | | | llvm-svn: 52960
* Implement suggestions from Chris:Owen Anderson2008-07-011-9/+10
| | | | | | | | - Use a more accurate heuristic for the size of the hashtable. - Use bitwise and instead of modulo since the size is a power of two. - Use new[] instead of malloc(). llvm-svn: 52951
* Replace the dynamically computed std::set lookup method for subregisters ↵Owen Anderson2008-07-011-1/+68
| | | | | | | | with a hashtable-based version that is computed by tblgen at the time LLVM is compiled. llvm-svn: 52945
OpenPOWER on IntegriCloud