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path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
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* Delete dead code. Nothing ever instantiates this.Jim Grosbach2011-10-271-4/+0
| | | | llvm-svn: 143153
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-221-6/+8
| | | | | | correctness along the way. llvm-svn: 142726
* Remove the TRI::getSubRegisterRegClass() hook.Jakob Stoklund Olesen2011-10-061-27/+2
| | | | | | | | | | | | | | | | This restores my karma after I added TRI::getSubClassWithSubReg(). Register constraints are applied 'backwards'. Starting from the register class required by an instruction operand, the correct question is: 'How can I constrain the super-register register class so all its sub-registers satisfy the instruction constraint?' The getMatchingSuperRegClass() hook answers that. We never need to go 'forwards': Starting from a super-register register class, what register class are the sub-registers in? The getSubRegisterRegClass() hook did that. llvm-svn: 141258
* Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen2011-10-051-0/+40
| | | | | | | | | | | | | | | | This function is used to constrain a register class to a sub-class that supports the given sub-register index. For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD. The function will be used to compute register classes when emitting INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation of sub-register operations. The version provided by TableGen is usually adequate, but targets can override. llvm-svn: 141142
* TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen2011-10-041-21/+11
| | | | | | | | When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. llvm-svn: 141081
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Store sub-class lists as a bit vector.Jakob Stoklund Olesen2011-09-301-21/+4
| | | | | | | | | | | | | | This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. llvm-svn: 140898
* Extract a slightly more general BitVector printer.Jakob Stoklund Olesen2011-09-301-7/+16
| | | | | | This one can also print 32-bit groups. llvm-svn: 140897
* Compute lists of super-classes in CodeGenRegisterClass.Jakob Stoklund Olesen2011-09-301-39/+19
| | | | | | | Use these lists instead of computing them on the fly in RegisterInfoEmitter. llvm-svn: 140895
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-28/+24
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Unconstify InitsDavid Greene2011-07-291-1/+1
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-1/+1
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-271-0/+3
| | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
* We always bounds check the bit set, there is no need to emit zero bytes at ↵Benjamin Kramer2011-07-231-13/+10
| | | | | | the end. llvm-svn: 135841
* Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This ↵Benjamin Kramer2011-07-231-1/+39
| | | | | | | | should be faster and smaller. Goodbye static ctors and dtors! llvm-svn: 135836
* Give TargetRegisterClass a pointer to the MCRegisterClass and use it to ↵Benjamin Kramer2011-07-231-32/+18
| | | | | | | | | access its data. This makes TargetRegisterClass slightly slower. Next step will be making contains faster. Eventually TargetRegisterClass will be killed entirely. llvm-svn: 135835
* Use the enum value for RegClassIDs.Benjamin Kramer2011-07-221-2/+4
| | | | llvm-svn: 135816
* Remove unused variables.Benjamin Kramer2011-07-221-4/+0
| | | | llvm-svn: 135768
* Teach tblgen to emit MCRegisterClasses.Benjamin Kramer2011-07-221-2/+54
| | | | | | - This currently introduces more instances of the static DenseSet dtor, but that should be fixable. llvm-svn: 135735
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-98/+125
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Migrate LLVM and Clang to use the new makeArrayRef(...) functions where ↵Frits van Bommel2011-07-181-2/+2
| | | | | | | | previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. llvm-svn: 135390
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-151-1/+1
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-9/+12
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-1/+1
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-1/+1
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-5/+3
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-7/+7
| | | | llvm-svn: 134027
* Alternative name enum should go into the enum portion.Evan Cheng2011-06-281-14/+21
| | | | llvm-svn: 133979
* Add support for alternative register names, useful for instructions whose ↵Owen Anderson2011-06-271-0/+12
| | | | | | | | operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
* More refactoring. MC doesn't need know about subreg indices.Evan Cheng2011-06-271-78/+79
| | | | llvm-svn: 133927
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-111/+150
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Remove dead typedefs.Evan Cheng2011-06-251-3/+0
| | | | llvm-svn: 133851
* Rename TargetRegisterDesc to MCRegisterDescEvan Cheng2011-06-241-2/+2
| | | | llvm-svn: 133845
* - Add MCRegisterInfo registration machinery. Also added x86 registration ↵Evan Cheng2011-06-241-2/+2
| | | | | | | | routines. - Rename TargetRegisterDesc to MCRegisterDesc. llvm-svn: 133820
* Make the generated InitXXXMCRegisterInfo function "static inline", so it ↵Benjamin Kramer2011-06-241-1/+1
| | | | | | | | | doesn't get emitted into multiple object files. This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen into a single binary (for example when building a monolithic libLLVM shared library). llvm-svn: 133791
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-241-70/+115
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-181-16/+16
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
* Remove MethodProtos/MethodBodies and allocation_order_begin/end.Jakob Stoklund Olesen2011-06-181-2/+1
| | | | | | | | | | | | | | Targets that need to change the default allocation order should use the AltOrders mechanism instead. See the X86 and ARM targets for examples. The allocation_order_begin() and allocation_order_end() methods have been replaced with getRawAllocationOrder(), and there is further support functions in RegisterClassInfo. It is no longer possible to insert arbitrary code into generated register classes. This is a feature. llvm-svn: 133332
* Provide AltOrders for specifying alternative allocation orders.Jakob Stoklund Olesen2011-06-181-4/+29
| | | | | | | | | | | | A register class can define AltOrders and AltOrderSelect instead of defining method protos and bodies. The AltOrders lists can be defined with set operations, and TableGen can verify that the alternative allocation orders only contain valid registers. This is currently an opt-in feature, and it is still possible to override allocation_order_begin/end. That will not be true for long. llvm-svn: 133320
* Replace the statically generated hashtables for checking register ↵Owen Anderson2011-06-151-88/+1
| | | | | | | | | relationships with just scanning the (typically tiny) static lists. At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries. Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan. With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time. It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables. llvm-svn: 133051
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-6/+8
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* Fix a compile time regression caused by too small hash tables.Jakob Stoklund Olesen2011-06-141-3/+16
| | | | | | | | | | | | | | Measure the worst case number of probes for a miss instead of the less conservative number of probes required for an insertion. Lower the limit to < 6 probes worst case. This doubles the size of the ARM and X86 hash tables, other targets are unaffected. LiveVariables runs 12% faster with this change. <rdar://problem/9598545> llvm-svn: 132999
* Tweak hash function and compress hash tables.Jakob Stoklund Olesen2011-06-121-19/+24
| | | | | | | | | | | | | | | | | Make the hash tables as small as possible while ensuring that all lookups can be done in less than 8 probes. Cut the aliases hash table in half by only storing a < b pairs - it is a symmetric relation. Use larger multipliers on the initial hash function to ensure that it properly covers the whole table, and to resolve some clustering in the very regular ARM register bank. This reduces the size of most of these tables by 4x - 8x. For instance, the ARM tables shrink from 48 KB to 8 KB. llvm-svn: 132888
* Remove now dead code.Jakob Stoklund Olesen2011-06-121-85/+0
| | | | | | These computations have been moved to CodeGenRegisters.cpp. llvm-svn: 132887
* Extract the generateHashTable function.Jakob Stoklund Olesen2011-06-121-144/+61
| | | | | | | | | | | The constant hash tables for sub-registers and overlaps are generated the same way, so extract a function to generate and print the hash table. Also use the information computed by CodeGenRegisters.cpp instead of the locally data. llvm-svn: 132886
* Compute lists of sub-regs, super-regs, and overlapping regs.Jakob Stoklund Olesen2011-06-121-54/+31
| | | | | | | | | | | | | | | | | | | | | | | Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. llvm-svn: 132881
* Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen2011-06-111-165/+9
| | | | | | | Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. llvm-svn: 132865
* Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen2011-06-101-8/+10
| | | | | | | Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. llvm-svn: 132849
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-13/+12
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-0/+29
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
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