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path: root/llvm/utils/TableGen/RegisterBankEmitter.cpp
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* [TableGen] Fix some mismatches in the use of Namespace fields versus Target ↵Craig Topper2017-07-071-1/+1
| | | | | | | | | | | | name in some of our emitters. Some of our emitters were using the name of the Target to reference things that were created by others emitters using Namespace. Apparently all targets have the same Target name as their instruction and register Namespace field? Someone on IRC had a target that didn't do this and was getting build errors. This patch is a necessary, but maybe not sufficient fix. llvm-svn: 307358
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-311-1/+1
| | | | | | instead of a std::string. llvm-svn: 304347
* TableGen: Fix infinite recursion in RegisterBankEmitterTom Stellard2017-01-301-3/+11
| | | | | | | | | | | | | | | | Summary: AMDGPU has two register classes with the same set of registers, and this was causing this tablegen backend would get stuck in infinite recursion. Reviewers: dsanders Reviewed By: dsanders Subscribers: tpr, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D29049 llvm-svn: 293483
* [globalisel] Fix an unused variable warning when NDEBUG is defined.Daniel Sanders2017-01-201-1/+1
| | | | llvm-svn: 292653
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-191-0/+312
| | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
* Re-revert: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-181-309/+0
| | | | | | | More missing guards. My build didn't notice it due to a stale file left over from a Global ISel build. llvm-svn: 292369
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-181-0/+309
| | | | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since last commit: The new tablegen pass is now correctly guarded by LLVM_BUILD_GLOBAL_ISEL and this should fix the buildbots however it may not be the whole fix. The previous buildbot failures suggest there may be a memory bug lurking that I'm unable to reproduce (including when using asan) or spot in the source. If they re-occur on this commit then I'll need assistance from the bot owners to track it down. Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292367
* Revert r292132: [globalisel] Tablegen-erate current Register Bank ↵Daniel Sanders2017-01-161-309/+0
| | | | | | | | | Information'... Several buildbots encountered a crash in tablegen when building this commit. Reverting while I investigate the cause. llvm-svn: 292136
* [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-161-0/+309
Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292132
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