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* [Tablegen][MCInstPredicate] Removed redundant template argument from class ↵Andrea Di Biagio2018-08-141-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | TIIPredicate, and implemented verification rules for TIIPredicates. This patch removes redundant template argument `TargetName` from TIIPredicate. Tablegen can always infer the target name from the context. So we don't need to force users of TIIPredicate to always specify it. This allows us to better modularize the tablegen class hierarchy for the so-called "function predicates". class FunctionPredicateBase has been added; it is currently used as a building block for TIIPredicates. However, I plan to reuse that class to model other function predicate classes too (i.e. not just TIIPredicates). For example, this can be a first step towards implementing proper support for dependency breaking instructions in tablegen. This patch also adds a verification step on TIIPredicates in tablegen. We cannot have multiple TIIPredicates with the same name. Otherwise, this will cause build errors later on, when tablegen'd .inc files are included by cpp files and then compiled. Differential Revision: https://reviews.llvm.org/D50708 llvm-svn: 339706
* [Tablegen] Replace uses of formatted_raw_ostream with raw_ostream in the ↵Andrea Di Biagio2018-08-131-26/+29
| | | | | | | | | | | | | | | | | | | | | | predicate expander. NFCI This is a follow-up of r339552. As pointed out by Craig in D50566, we don't need a formatted_raw_ostream to indent strings. We can use instead raw_ostream::indent(). Internally, class PredicateExpander already keeps track of the current indentation level. Also, the grammar for predicates is well parenthesized, and therefore we don't need to use a formatted_raw_ostream to continuously track the column number. Instead we can safely replace all the uses of formatted_raw_ostream::PadToColumn() with uses of raw_ostream::indent(). By replacing formatted_raw_ostream with a simpler raw_ostream, we also avoid the implicit check on the newline character on every print to stream. No functional change intended. llvm-svn: 339577
* [MC][PredicateExpander] Extend the grammar to support simple switch and ↵Andrea Di Biagio2018-08-091-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | return statements. This patch introduces tablegen class MCStatement. Currently, an MCStatement can be either a return statement, or a switch statement. ``` MCStatement: MCReturnStatement MCOpcodeSwitchStatement ``` A MCReturnStatement expands to a return statement, and the boolean expression associated with the return statement is described by a MCInstPredicate. An MCOpcodeSwitchStatement is a switch statement where the condition is a check on the machine opcode. It allows the definition of multiple checks, as well as a default case. More details on the grammar implemented by these two new constructs can be found in the diff for TargetInstrPredicates.td. This patch makes it easier to read the body of auto-generated TargetInstrInfo predicates. In future, I plan to reuse/extend the MCStatement grammar to describe more complex target hooks. For now, this is just a first step (mostly a minor cosmetic change to polish the new predicates framework). Differential Revision: https://reviews.llvm.org/D50457 llvm-svn: 339352
* [cfi-verify] Support AArch64.Joel Galenson2018-07-131-0/+1
| | | | | | | | | | | | This patch adds support for AArch64 to cfi-verify. This required three changes to cfi-verify. First, it generalizes checking if an instruction is a trap by adding a new isTrap flag to TableGen (and defining it for x86 and AArch64). Second, the code that ensures that the operand register is not clobbered between the CFI check and the indirect call needs to allow a single dereference (in x86 this happens as part of the jump instruction). Third, we needed to ensure that return instructions are not counted as indirect branches. Technically, returns are indirect branches and can be covered by CFI, but LLVM's forward-edge CFI does not protect them, and x86 does not consider them, so we keep that behavior. In addition, we had to improve AArch64's code to evaluate the branch target of a MCInst to handle calls where the destination is not the first operand (which it often is not). Differential Revision: https://reviews.llvm.org/D48836 llvm-svn: 337007
* [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling ↵Andrea Di Biagio2018-05-251-0/+55
| | | | | | | | | | | | | | | | | | | | classes. This patch is the second of a sequence of three patches related to LLVM-dev RFC "MC support for varinat scheduling classes". https://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to enable the resolution of variant classes in MC with the help of a new method named `MCSubtargetInfo::resolveVariantSchedClass()`. This patch also teaches the SubtargetEmitter how to automatically generate the definition of method resolveVariantSchedClass(). That definition is emitted within a sub-class of MCSubtargetInfo named XXXGenMCSubtargetInfo (where XXX is the name of the Target). Differential Revision: https://reviews.llvm.org/D47077 llvm-svn: 333286
* [RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.Andrea Di Biagio2018-05-251-3/+32
| | | | | | | | | | | | | | | | | | | | | | This patch is the first of a sequence of three patches described by the LLVM-dev RFC "MC support for variant scheduling classes". http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to introduce a new class of scheduling predicates for SchedReadVariant and SchedWriteVariant. An MCSchedPredicate can be used instead of a normal SchedPredicate to model checks on the instruction (either a MachineInstr or a MCInst). Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition. MCInstPredicate allows the definition of expressions with a well-known semantic, that can be used to generate code for both MachineInstr and MCInst. This is the first step toward teaching to tools like lllvm-mca how to resolve variant scheduling classes. Differential Revision: https://reviews.llvm.org/D46695 llvm-svn: 333282
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-231-0/+1
| | | | | | | | | | | | | This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 llvm-svn: 333093
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [Targets] Don't automatically include the scheduler class enum from ↵Craig Topper2017-12-131-1/+9
| | | | | | | | | | *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately. Most of the targets don't need the scheduler class enum. I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86. llvm-svn: 320552
* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-071-6/+6
| | | | | | namespace. NFC llvm-svn: 307362
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-121-10/+14
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289475
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-1/+2
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-0/+1
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-1/+0
| | | | | | | hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-0/+1
| | | | | | | | | | | descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
* XRay: Add entry and exit sledsDean Michael Berris2016-07-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: In this patch we implement the following parts of XRay: - Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches. - Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts). - X86-specific nop sleds as described in the white paper. - A machine function pass that adds the different instrumentation marker instructions at a very late stage. - A way of identifying which return opcode is considered "normal" for each architecture. There are some caveats here: 1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet. 2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library. Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D19904 llvm-svn: 275367
* [TableGen] Use range-based for loop. NFCCraig Topper2016-02-161-2/+2
| | | | llvm-svn: 260928
* [TableGen] Don't call emitSourceFileHeader a second time in the middle of ↵Craig Topper2016-02-111-3/+1
| | | | | | the output file. llvm-svn: 260501
* [TableGen] Whitespace cleanup in output file. NFCCraig Topper2016-02-111-14/+14
| | | | llvm-svn: 260500
* [TableGen] Simplify code slightly. NFCCraig Topper2016-02-111-6/+3
| | | | llvm-svn: 260499
* [TableGen] Store result of getInstructionsByEnumValue in an ArrayRef instead ↵Craig Topper2016-02-011-6/+6
| | | | | | of accidentally copying to a vector. llvm-svn: 259336
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper2016-01-171-2/+2
| | | | | | to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-051-1/+1
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* [WinEH] Make FuncletLayout more robust against catchretDavid Majnemer2015-10-011-3/+3
| | | | | | | | | Catchret transfers control from a catch funclet to an earlier funclet. However, it is not completely clear which funclet the catchret target is part of. Make this clear by stapling the catchret target's funclet membership onto the CATCHRET SDAG node. llvm-svn: 249052
* Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor ↵Hans Wennborg2015-09-101-22/+20
| | | | | | | | | fixes" Except the changes that defined virtual destructors as =default, because that ran into problems with GCC 4.7 and overriding methods that weren't noexcept. llvm-svn: 247298
* Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"Hans Wennborg2015-09-101-20/+22
| | | | | | | This caused build breakges, e.g. http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/24926 llvm-svn: 247226
* Fix Clang-tidy misc-use-override warnings, other minor fixesHans Wennborg2015-09-101-22/+20
| | | | | | | | Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D12740 llvm-svn: 247216
* Add support for the convergent flag at the MC and MachineInstr levels.Owen Anderson2015-05-281-31/+32
| | | | llvm-svn: 238450
* Expand the Flags field of MCInstrDesc to 64 bits, while simultaneouslyOwen Anderson2015-05-281-2/+2
| | | | | | | | | | | shrinking the Size and NumDefs fields to offset the size growth, and reordering the fields to preserve a good packing. This is necessary in the short term for adding a convergent flag, and simultaneously future-proofs us against more flags being added in the future. llvm-svn: 238445
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-4/+4
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-4/+4
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-4/+4
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Fix tablegen's PrintFatalError function to run registered fileJames Y Knight2015-05-111-4/+2
| | | | | | | | | | | | | | | cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-4/+4
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-4/+4
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Use the variable names from the TargetInstrInfo source when weEric Christopher2015-03-131-5/+7
| | | | | | | reference them in the generated files. A few characters aren't huge here and CFSetupOpcode is much more readable than S0. llvm-svn: 232132
* Add a return after the llvm namespace code for a little extraEric Christopher2015-03-131-3/+3
| | | | | | readability in generated files. llvm-svn: 232131
* Fix a couple of depedent->dependent typos.Eric Christopher2015-02-261-1/+1
| | | | llvm-svn: 230584
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-4/+4
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-4/+4
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* Target: Allow target specific operand typesTom Stellard2015-01-121-1/+1
| | | | | | | | | | | | | | | | | | | This adds two new fields to the RegisterOperand TableGen class: string OperandNamespace = "MCOI"; string OperandType = "OPERAND_REGISTER"; These fields can be used to specify a target specific operand type, which will be stored in the OperandType member of the MCOperandInfo object. This can be useful for targets that need to store some extra information about operands that cannot be expressed using the target independent types. For example, in the R600 backend, there are operands which can take either registers or immediates and it is convenient to be able to specify this in the TableGen definitions. llvm-svn: 225661
* Tablegen output formatting fixes.Craig Topper2014-11-231-2/+4
| | | | llvm-svn: 222633
* Add isInsertSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
* Add isExtractSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
* Add isRegSequence property.Quentin Colombet2014-08-111-0/+1
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* Make getNamedOperandIdx readonlyMatt Arsenault2014-08-011-0/+1
| | | | llvm-svn: 214524
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-301-5/+5
| | | | llvm-svn: 207611
* c++11: Tidy up tblgen w/ range loops.Jim Grosbach2014-04-181-62/+53
| | | | | | IntrInfoEmitter cleanup. llvm-svn: 206553
* Fix a vector that was passed by value instead of reference.Craig Topper2014-02-051-5/+5
| | | | llvm-svn: 200827
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-4/+6
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
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