summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/InstrInfoEmitter.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* TableGen: Generate a function for getting operand indices based on their ↵Tom Stellard2013-06-251-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined names This patch modifies TableGen to generate a function in ${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used to look up indices for operands based on their names. In order to activate this feature for an instruction, you must set the UseNamedOperandTable bit. For example, if you have an instruction like: def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>; You can look up the operand indices using the new function, like this: Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2 The operand names are case sensitive, so $dst and $DST are considered different operands. This change is useful for R600 which has instructions with a large number of operands, many of which model single bit instruction configuration values. These configuration bits are common across most instructions, but may have a different operand index depending on the instruction type. It is useful to have a convenient way to look up the operand indices, so these bits can be generically set on any instruction. llvm-svn: 184879
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-1/+1
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-2/+2
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-2/+4
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* add TableGen support to create relationship maps between instructionsSebastian Pop2012-10-251-0/+2
| | | | | | | | | | | Relationship maps are represented as InstrMapping records which are parsed by TableGen and the information is used to construct mapping tables to represent appropriate relations between instructions. These tables are emitted into XXXGenInstrInfo.inc file along with the functions to query them. Patch by Jyotsna Verma <jverma@codeaurora.org>. llvm-svn: 166685
* Change (!list.size() == 0) to (!list.empty()). No functional change.Richard Trieu2012-10-121-1/+1
| | | | llvm-svn: 165812
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-101-1/+1
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-2/+2
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-181-2/+1
| | | | llvm-svn: 164096
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-1/+2
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-171-2/+1
| | | | llvm-svn: 164063
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-161-0/+1
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-26/+6
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-4/+48
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Tidy up. Whitespace.Jim Grosbach2012-04-111-1/+1
| | | | llvm-svn: 154531
* Use SequenceToOffsetTable to create instruction name table. Saves space ↵Craig Topper2012-04-011-9/+16
| | | | | | particularly on X86 where AVX instructions just add a 'v' to the front of other instructions. llvm-svn: 153841
* Include cstdio in a few place that depended on getting it transitively ↵Benjamin Kramer2012-03-231-0/+1
| | | | | | through StringExtras.h llvm-svn: 153328
* Revert r152202: "Use uint16_t to store InstrNameIndices in MCInstrInfo."Jakob Stoklund Olesen2012-03-151-7/+5
| | | | | | | | We cannot limit the concatenated instruction names to 64K. ARM is already at 32K, and it is easy to imagine a target with more instructions. llvm-svn: 152817
* Shrink and reorder some fields in MCOperandInfo to fit it in 8 bytes to ↵Craig Topper2012-03-111-5/+5
| | | | | | reduce size of static tables. llvm-svn: 152524
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-1/+1
| | | | llvm-svn: 152301
* Re-commit r152202 hopefully fixing the MSVC linker error.Craig Topper2012-03-081-5/+7
| | | | | | | Original commit message: Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. llvm-svn: 152296
* Revert r152202 as it's causing internal buildbot failures.Chad Rosier2012-03-071-6/+4
| | | | | | | | | | Original commit message: Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. llvm-svn: 152233
* Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to ↵Craig Topper2012-03-071-4/+6
| | | | | | protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. llvm-svn: 152202
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-101-2/+20
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. llvm-svn: 150245
* Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per ↵Benjamin Kramer2012-02-091-2/+3
| | | | | | | | entry on x86_64. No change on i386. llvm-svn: 150170
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-221-2/+2
| | | | | | correctness along the way. llvm-svn: 142726
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Add target hook for pseudo instruction expansion.Jakob Stoklund Olesen2011-09-251-0/+1
| | | | | | | | | | | | Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. llvm-svn: 140472
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-1/+2
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-2/+1
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* Follow up to r138791.Evan Cheng2011-08-301-0/+1
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Unconstify InitsDavid Greene2011-07-291-4/+4
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-4/+4
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-151-1/+1
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* Add a new field to MCOperandInfo that contains information about the type of ↵Benjamin Kramer2011-07-141-0/+5
| | | | | | | | | | the Operand. - The actual values are from the MCOI::OperandType enum. - Teach tblgen to read it from the instruction definition. - This is a better implementation of the hacks in edis. llvm-svn: 135197
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-2/+2
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson2011-07-131-2/+4
| | | | | | an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-4/+4
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-4/+4
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-2/+2
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-1/+25
| | | | llvm-svn: 134244
* Add MCInstrInfo registeration machinery.Evan Cheng2011-06-281-1/+9
| | | | llvm-svn: 134026
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+43
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-33/+33
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Remove RCBarriers from TargetInstrDesc.Evan Cheng2011-06-271-55/+1
| | | | llvm-svn: 133964
* Add support for alternative register names, useful for instructions whose ↵Owen Anderson2011-06-271-16/+18
| | | | | | | | operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-4/+4
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* - Add "Bitcast" target instruction property for instructions which performEvan Cheng2011-03-151-0/+1
| | | | | | | nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. llvm-svn: 127667
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-16/+16
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
OpenPOWER on IntegriCloud