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path: root/llvm/utils/TableGen/InstrInfoEmitter.cpp
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* Move M_* flags down in the file. Move SchedClass up in the Chris Lattner2008-01-071-2/+2
| | | | | | | TargetInstrDescriptor class and shrink to 16-bits, saving a word in TargetInstrDescriptor. Add some comments. llvm-svn: 45686
* the name field of instructions is never set to a non-empty string, Chris Lattner2008-01-071-3/+3
| | | | | | just unconditionally use the def name of the instruction. llvm-svn: 45684
* Add predicates methods to TargetOperandInfo, and switch all clients Chris Lattner2008-01-071-3/+3
| | | | | | | over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. llvm-svn: 45677
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-2/+2
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-16/+17
| | | | llvm-svn: 45656
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-10/+22
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* set the 'isstore' flag for instructions whose pattern is an Chris Lattner2008-01-061-1/+8
| | | | | | intrinsic that writes to memory. llvm-svn: 45650
* remove some old hacky code that tried to infer whether a store Chris Lattner2008-01-061-19/+49
| | | | | | | | | | | occured in a pattern, but failed miserably. The new code works for any instruction that has a store in its pattern, including all the x86 mem op mem instructions. The only target-independent code that uses this is branch folding, so this won't change anything in practice. llvm-svn: 45648
* rearrange some code to allow inferring instr info from the pattern of the ↵Chris Lattner2008-01-061-34/+52
| | | | | | instr, but don't do so yet. llvm-svn: 45647
* final cleanups.Chris Lattner2008-01-061-4/+4
| | | | llvm-svn: 45644
* further simplifications and cleanupChris Lattner2008-01-061-37/+57
| | | | llvm-svn: 45643
* simplify some codeChris Lattner2008-01-061-16/+8
| | | | llvm-svn: 45642
* split enum emission out from InstrInfoEmitter into it's own tblgen backend.Chris Lattner2008-01-061-36/+0
| | | | llvm-svn: 45640
* tblgen shouldn't include headers from llvm codegen.Chris Lattner2007-12-301-3/+3
| | | | llvm-svn: 45429
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-2/+3
| | | | | | side effects for machine instructions. llvm-svn: 45022
* Oops. Forgot these.Evan Cheng2007-12-131-0/+1
| | | | llvm-svn: 44969
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* Added TargetInstrDescriptor::numDefs - num of results.Evan Cheng2007-08-021-1/+2
| | | | llvm-svn: 40709
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-1/+3
| | | | | | MBB's. PR1350 llvm-svn: 40518
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-101-1/+6
| | | | llvm-svn: 38498
* ImmutablePredicateOperand is no more.Evan Cheng2007-07-061-2/+1
| | | | llvm-svn: 37963
* Instructions with ImmutablePredicateOperand aren't really predicable since ↵Evan Cheng2007-07-051-1/+2
| | | | | | their predicates are fixed at isel time. llvm-svn: 37899
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | llvm-svn: 37643
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-061-0/+1
| | | | | | are used to predicate instructions. llvm-svn: 37465
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-161-1/+1
| | | | | | without having a PredicateOperand. llvm-svn: 37116
* Mark all (not just the first) predicate operand M_PREDICATE_OPERAND.Evan Cheng2007-05-151-1/+1
| | | | llvm-svn: 37061
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35159
* Files missing from LABEL check in.Jim Laskey2007-01-261-1/+3
| | | | llvm-svn: 33539
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-2/+2
| | | | llvm-svn: 32333
* Add opcode to TargetInstrDescriptor.Evan Cheng2006-11-171-3/+4
| | | | llvm-svn: 31804
* ADd support for adding constraints to suboperandsChris Lattner2006-11-151-1/+1
| | | | llvm-svn: 31748
* allow ptr_rc to explicitly appear in an instructions operand list, it doesn'tChris Lattner2006-11-101-37/+40
| | | | | | have to be a subpart of a complex operand. llvm-svn: 31618
* Remove M_2_ADDR_FLAG.Evan Cheng2006-11-091-1/+0
| | | | llvm-svn: 31583
* Mark predicate operands as such in operand info.Chris Lattner2006-11-061-0/+4
| | | | llvm-svn: 31483
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-061-40/+44
| | | | | | to extend. llvm-svn: 31481
* recognize ppc's blr instruction as predicatedChris Lattner2006-11-061-0/+1
| | | | llvm-svn: 31480
* Clean up some code.Evan Cheng2006-11-041-1/+2
| | | | llvm-svn: 31451
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-011-14/+27
| | | | llvm-svn: 31333
* Eliminate data relocations by using NULL instead of global empty list.Jim Laskey2006-07-211-5/+2
| | | | llvm-svn: 29250
* Use an enumeration to eliminate data relocations.Jim Laskey2006-07-211-1/+1
| | | | llvm-svn: 29249
* Instructions with variable operands (variable_ops) can have a number requiredEvan Cheng2006-06-151-10/+7
| | | | | | | | | | | | | operands. e.g. def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops), "call {*}$dst", [(X86call GR32:$dst)]>; TableGen should emit operand informations for the "required" operands. Added a target instruction info flag M_VARIABLE_OPS to indicate the target instruction may have more operands in addition to the minimum required operands. llvm-svn: 28791
* lib/Target/Target.tdEvan Cheng2006-05-181-5/+7
| | | | llvm-svn: 28386
* Noop instructionEvan Cheng2006-05-121-2/+0
| | | | llvm-svn: 28241
* Set isStore of instructions with ISD::TRUNCSTORE root node.Evan Cheng2006-05-031-3/+5
| | | | llvm-svn: 28075
* Put instruction names into the first non TargetInstrInfo namespace found.Chris Lattner2006-05-011-10/+18
| | | | llvm-svn: 28043
* FormatingEvan Cheng2006-05-011-1/+1
| | | | llvm-svn: 28036
* Mark instructions whose pattern is (store ...) isStore.Evan Cheng2006-05-011-1/+17
| | | | llvm-svn: 28032
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