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* Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson2010-09-231-1/+0
| | | | | | | | instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! llvm-svn: 114710
* Add an TargetInstrDesc bit to indicate that a given instruction is a ↵Owen Anderson2010-09-231-0/+1
| | | | | | | | conditional move. Not intended functionality change, as nothing uses this yet. llvm-svn: 114702
* Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling2010-08-081-0/+1
| | | | | | useful after all. llvm-svn: 110531
* Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling2010-08-061-1/+0
| | | | | | | | | | | | | need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h llvm-svn: 110424
* Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling2010-07-301-0/+1
| | | | | | | later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. llvm-svn: 109901
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-1/+2
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* How about ULL...Eric Christopher2010-06-091-1/+1
| | | | llvm-svn: 105726
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-1/+1
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-72/+12
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* Teach TableGen to understand X.Y notation in the TSFlagsFields strings.Jakob Stoklund Olesen2010-03-251-1/+1
| | | | | | | Remove much horribleness from X86InstrFormats as a result. Similar simplifications are probably possible for other targets. llvm-svn: 99539
* Finally change the instruction looking map to be a densemap fromChris Lattner2010-03-191-7/+1
| | | | | | | | | record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). llvm-svn: 98916
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-2/+2
| | | | | | Use CodeGenTarget::getInstNamespace in one place and fix it. llvm-svn: 98915
* revert 98912Chris Lattner2010-03-191-2/+2
| | | | llvm-svn: 98914
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-2/+2
| | | | llvm-svn: 98912
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-2/+2
| | | | | | | to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
* Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner2010-02-101-1/+14
| | | | | | | | | for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). llvm-svn: 95753
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-1/+1
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen2010-01-151-2/+1
| | | | | | Also, DEBUG_VALUE has side effects. llvm-svn: 93498
* Add DEBUG_DECLARE. Not used yet.Dale Johannesen2010-01-091-1/+2
| | | | llvm-svn: 93040
* Add DEBUG_VALUE. Not used yet.Dale Johannesen2010-01-081-1/+2
| | | | llvm-svn: 93030
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-2/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng2009-10-011-0/+2
| | | | | | | | | | set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. llvm-svn: 83196
* Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen2009-09-281-1/+1
| | | | | | | | | | unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. llvm-svn: 83006
* prune the #includes in raw_ostream.h by moving a Chris Lattner2009-08-241-0/+1
| | | | | | | member out of line. ftostr is not particularly speedy, so that method is presumably not perf sensitive. llvm-svn: 79885
* 1. Introduce a new TargetOperandInfo::getRegClass() helper methodChris Lattner2009-07-291-0/+3
| | | | | | | | | | | | | and convert code to using it, instead of having lots of things poke the isLookupPtrRegClass() method directly. 2. Make PointerLikeRegClass contain a 'kind' int, and store it in the existing regclass field of TargetOperandInfo when the isLookupPtrRegClass() predicate is set. Make getRegClass pass this into TargetRegisterInfo::getPointerRegClass(), allowing targets to have multiple ptr_rc things. llvm-svn: 77504
* make ptr_rc derive from a new PointerLikeRegClass tblgen class.Chris Lattner2009-07-291-1/+1
| | | | llvm-svn: 77503
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-8/+7
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-1/+1
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-1/+2
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-1/+1
| | | | llvm-svn: 60487
* Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ↵Evan Cheng2008-10-171-1/+55
| | | | | | | | instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. TableGen has been taught to generate the lists from instruction definitions. llvm-svn: 57722
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-1/+3
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman2008-05-311-12/+0
| | | | | | | | | | | index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. llvm-svn: 51808
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-291-0/+12
| | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-281-13/+14
| | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. llvm-svn: 51660
* Move instruction flag inference out of InstrInfoEmitter and intoDan Gohman2008-04-031-133/+4
| | | | | | | | | | | | CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. llvm-svn: 49123
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-1/+2
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-1/+0
| | | | llvm-svn: 48381
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-1/+2
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner2008-01-101-2/+1
| | | | | | | | | | | | | | | | both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. llvm-svn: 45843
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-22/+33
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* if an instr lacks a pattern, assume it has side effects (unless never has ↵Chris Lattner2008-01-101-1/+4
| | | | | | s-e is true). llvm-svn: 45823
* start inferring 'no side effects'.Chris Lattner2008-01-101-54/+57
| | | | llvm-svn: 45822
* Infer mayloadChris Lattner2008-01-101-3/+13
| | | | llvm-svn: 45819
* realize that instructions who match intrinsics that read memory read memory.Chris Lattner2008-01-101-3/+12
| | | | | | Also, instructions with any nodes that are SDNPMayLoad also read memory. llvm-svn: 45817
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-081-12/+12
| | | | | | This is currently not set by anything. llvm-svn: 45748
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Rename all the M_* flags to be namespace qualified enums, and switch Chris Lattner2008-01-071-25/+25
| | | | | | | | all clients over to using predicates instead of these flags directly. These are now private values which are only to be used to statically initialize the tables. llvm-svn: 45692
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-071-3/+3
| | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. llvm-svn: 45687
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