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* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-4/+4
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Use the variable names from the TargetInstrInfo source when weEric Christopher2015-03-131-5/+7
| | | | | | | reference them in the generated files. A few characters aren't huge here and CFSetupOpcode is much more readable than S0. llvm-svn: 232132
* Add a return after the llvm namespace code for a little extraEric Christopher2015-03-131-3/+3
| | | | | | readability in generated files. llvm-svn: 232131
* Fix a couple of depedent->dependent typos.Eric Christopher2015-02-261-1/+1
| | | | llvm-svn: 230584
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-4/+4
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-4/+4
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* Target: Allow target specific operand typesTom Stellard2015-01-121-1/+1
| | | | | | | | | | | | | | | | | | | This adds two new fields to the RegisterOperand TableGen class: string OperandNamespace = "MCOI"; string OperandType = "OPERAND_REGISTER"; These fields can be used to specify a target specific operand type, which will be stored in the OperandType member of the MCOperandInfo object. This can be useful for targets that need to store some extra information about operands that cannot be expressed using the target independent types. For example, in the R600 backend, there are operands which can take either registers or immediates and it is convenient to be able to specify this in the TableGen definitions. llvm-svn: 225661
* Tablegen output formatting fixes.Craig Topper2014-11-231-2/+4
| | | | llvm-svn: 222633
* Add isInsertSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
* Add isExtractSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
* Add isRegSequence property.Quentin Colombet2014-08-111-0/+1
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* Make getNamedOperandIdx readonlyMatt Arsenault2014-08-011-0/+1
| | | | llvm-svn: 214524
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-301-5/+5
| | | | llvm-svn: 207611
* c++11: Tidy up tblgen w/ range loops.Jim Grosbach2014-04-181-62/+53
| | | | | | IntrInfoEmitter cleanup. llvm-svn: 206553
* Fix a vector that was passed by value instead of reference.Craig Topper2014-02-051-5/+5
| | | | llvm-svn: 200827
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-4/+6
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-6/+4
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.Ahmed Bougacha2013-11-171-0/+31
| | | | llvm-svn: 194978
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-4/+6
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+13
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* TableGen: Enumerate Schedule Model too.Vincent Lejeune2013-09-031-1/+9
| | | | llvm-svn: 189839
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-221-2/+2
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* Revert "TableGen: Enumerate Schedule Model too."Tom Stellard2013-07-311-7/+0
| | | | | | This reverts commit 2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0. llvm-svn: 187525
* TableGen: Enumerate Schedule Model too.Vincent Lejeune2013-07-311-0/+7
| | | | llvm-svn: 187511
* Teaching llvm-tblgen to not emit a switch statement when there are no case ↵Aaron Ballman2013-07-151-23/+30
| | | | | | statements. llvm-svn: 186330
* TableGen: Generate a function for getting operand indices based on their ↵Tom Stellard2013-06-251-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined names This patch modifies TableGen to generate a function in ${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used to look up indices for operands based on their names. In order to activate this feature for an instruction, you must set the UseNamedOperandTable bit. For example, if you have an instruction like: def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>; You can look up the operand indices using the new function, like this: Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2 The operand names are case sensitive, so $dst and $DST are considered different operands. This change is useful for R600 which has instructions with a large number of operands, many of which model single bit instruction configuration values. These configuration bits are common across most instructions, but may have a different operand index depending on the instruction type. It is useful to have a convenient way to look up the operand indices, so these bits can be generically set on any instruction. llvm-svn: 184879
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-1/+1
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-2/+2
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-2/+4
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* add TableGen support to create relationship maps between instructionsSebastian Pop2012-10-251-0/+2
| | | | | | | | | | | Relationship maps are represented as InstrMapping records which are parsed by TableGen and the information is used to construct mapping tables to represent appropriate relations between instructions. These tables are emitted into XXXGenInstrInfo.inc file along with the functions to query them. Patch by Jyotsna Verma <jverma@codeaurora.org>. llvm-svn: 166685
* Change (!list.size() == 0) to (!list.empty()). No functional change.Richard Trieu2012-10-121-1/+1
| | | | llvm-svn: 165812
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-101-1/+1
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-2/+2
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-181-2/+1
| | | | llvm-svn: 164096
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-1/+2
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-171-2/+1
| | | | llvm-svn: 164063
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-161-0/+1
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-26/+6
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-4/+48
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Tidy up. Whitespace.Jim Grosbach2012-04-111-1/+1
| | | | llvm-svn: 154531
* Use SequenceToOffsetTable to create instruction name table. Saves space ↵Craig Topper2012-04-011-9/+16
| | | | | | particularly on X86 where AVX instructions just add a 'v' to the front of other instructions. llvm-svn: 153841
* Include cstdio in a few place that depended on getting it transitively ↵Benjamin Kramer2012-03-231-0/+1
| | | | | | through StringExtras.h llvm-svn: 153328
* Revert r152202: "Use uint16_t to store InstrNameIndices in MCInstrInfo."Jakob Stoklund Olesen2012-03-151-7/+5
| | | | | | | | We cannot limit the concatenated instruction names to 64K. ARM is already at 32K, and it is easy to imagine a target with more instructions. llvm-svn: 152817
* Shrink and reorder some fields in MCOperandInfo to fit it in 8 bytes to ↵Craig Topper2012-03-111-5/+5
| | | | | | reduce size of static tables. llvm-svn: 152524
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-1/+1
| | | | llvm-svn: 152301
* Re-commit r152202 hopefully fixing the MSVC linker error.Craig Topper2012-03-081-5/+7
| | | | | | | Original commit message: Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. llvm-svn: 152296
* Revert r152202 as it's causing internal buildbot failures.Chad Rosier2012-03-071-6/+4
| | | | | | | | | | Original commit message: Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. llvm-svn: 152233
* Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to ↵Craig Topper2012-03-071-4/+6
| | | | | | protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. llvm-svn: 152202
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-101-2/+20
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. llvm-svn: 150245
* Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per ↵Benjamin Kramer2012-02-091-2/+3
| | | | | | | | entry on x86_64. No change on i386. llvm-svn: 150170
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