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path: root/llvm/utils/TableGen/InstrInfoEmitter.cpp
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* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | llvm-svn: 37643
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-061-0/+1
| | | | | | are used to predicate instructions. llvm-svn: 37465
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-161-1/+1
| | | | | | without having a PredicateOperand. llvm-svn: 37116
* Mark all (not just the first) predicate operand M_PREDICATE_OPERAND.Evan Cheng2007-05-151-1/+1
| | | | llvm-svn: 37061
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35159
* Files missing from LABEL check in.Jim Laskey2007-01-261-1/+3
| | | | llvm-svn: 33539
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-2/+2
| | | | llvm-svn: 32333
* Add opcode to TargetInstrDescriptor.Evan Cheng2006-11-171-3/+4
| | | | llvm-svn: 31804
* ADd support for adding constraints to suboperandsChris Lattner2006-11-151-1/+1
| | | | llvm-svn: 31748
* allow ptr_rc to explicitly appear in an instructions operand list, it doesn'tChris Lattner2006-11-101-37/+40
| | | | | | have to be a subpart of a complex operand. llvm-svn: 31618
* Remove M_2_ADDR_FLAG.Evan Cheng2006-11-091-1/+0
| | | | llvm-svn: 31583
* Mark predicate operands as such in operand info.Chris Lattner2006-11-061-0/+4
| | | | llvm-svn: 31483
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-061-40/+44
| | | | | | to extend. llvm-svn: 31481
* recognize ppc's blr instruction as predicatedChris Lattner2006-11-061-0/+1
| | | | llvm-svn: 31480
* Clean up some code.Evan Cheng2006-11-041-1/+2
| | | | llvm-svn: 31451
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-011-14/+27
| | | | llvm-svn: 31333
* Eliminate data relocations by using NULL instead of global empty list.Jim Laskey2006-07-211-5/+2
| | | | llvm-svn: 29250
* Use an enumeration to eliminate data relocations.Jim Laskey2006-07-211-1/+1
| | | | llvm-svn: 29249
* Instructions with variable operands (variable_ops) can have a number requiredEvan Cheng2006-06-151-10/+7
| | | | | | | | | | | | | operands. e.g. def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops), "call {*}$dst", [(X86call GR32:$dst)]>; TableGen should emit operand informations for the "required" operands. Added a target instruction info flag M_VARIABLE_OPS to indicate the target instruction may have more operands in addition to the minimum required operands. llvm-svn: 28791
* lib/Target/Target.tdEvan Cheng2006-05-181-5/+7
| | | | llvm-svn: 28386
* Noop instructionEvan Cheng2006-05-121-2/+0
| | | | llvm-svn: 28241
* Set isStore of instructions with ISD::TRUNCSTORE root node.Evan Cheng2006-05-031-3/+5
| | | | llvm-svn: 28075
* Put instruction names into the first non TargetInstrInfo namespace found.Chris Lattner2006-05-011-10/+18
| | | | llvm-svn: 28043
* FormatingEvan Cheng2006-05-011-1/+1
| | | | llvm-svn: 28036
* Mark instructions whose pattern is (store ...) isStore.Evan Cheng2006-05-011-1/+17
| | | | llvm-svn: 28032
* Don't fill in fields that no longer exist.Chris Lattner2006-04-201-2/+1
| | | | llvm-svn: 27898
* If we want to emit things in enum order, use getInstructionsByEnumValue toChris Lattner2006-01-271-15/+25
| | | | | | | | | | get the order, don't compute it ourselves. Don't emit stuff like (14<<0), emit 14 instead. Don't attempt to get target properties for builtin instructions. llvm-svn: 25672
* almost got the HP-UX tester up.. :)Duraid Madina2005-12-301-1/+1
| | | | llvm-svn: 25051
* Teach tblgen about instruction operands that have multiple MachineInstrChris Lattner2005-11-191-6/+16
| | | | | | | operands, digging into them to find register values (used on X86). Patch by Evan Cheng! llvm-svn: 24424
* Allow itineraries to be passed through the Target Machine.Jim Laskey2005-11-011-1/+1
| | | | llvm-svn: 24139
* Keep VC++ happy.Jeff Cohen2005-11-011-0/+1
| | | | llvm-svn: 24137
* Emit itinerary class in instruction info.Jim Laskey2005-10-311-1/+33
| | | | llvm-svn: 24122
* Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)Chris Lattner2005-10-281-30/+15
| | | | llvm-svn: 24074
* spell this variable rightChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23095
* Expose a new flag to TargetInstrInfoChris Lattner2005-08-261-0/+2
| | | | llvm-svn: 23094
* add a marker at the end of the instruction enum listChris Lattner2005-08-261-0/+1
| | | | llvm-svn: 23090
* Emit this:Chris Lattner2005-08-191-2/+1
| | | | | | | | | | | | | static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, }; instead of this: static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, }; For operand information, which does not require dynamic (startup-time) initialization. llvm-svn: 22931
* Emit real operand info for instructions. This currently works but is badChris Lattner2005-08-191-10/+44
| | | | | | | in one way: the generated tables require dynamic initialization for the register classes. This will be fixed in a future patch. llvm-svn: 22919
* For now, just emit empty operand info structures.Chris Lattner2005-08-191-2/+23
| | | | llvm-svn: 22910
* now that all of the targets are clean w.r.t. the number of operands for eachChris Lattner2005-08-191-3/+11
| | | | | | | | instruction defined, actually emit this to the InstrInfoDescriptor, which allows an assert in the machineinstrbuilder to do some checking for us, and is required by the dag->dag emitter llvm-svn: 22895
* revert this change, which causes breakage, temporarilyChris Lattner2005-08-181-1/+3
| | | | llvm-svn: 22880
* When emitting implicit use/def lists, only emit each unique list once. ThoughChris Lattner2005-08-181-19/+42
| | | | | | | | | | | | LLVM is able to merge identical static const globals, GCC isn't, and this caused some bloat in the generated data. This has a marginal effect on PPC, shrinking the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger reduction. This should speed up the register allocator as well by reducing the dcache footprint for this static data. llvm-svn: 22879
* Fill in the numOperands field of the TargetInstrDescriptor struct from theChris Lattner2005-08-181-1/+1
| | | | | | .td file. llvm-svn: 22873
* Remove trailing whitespaceMisha Brukman2005-04-221-4/+4
| | | | llvm-svn: 21428
* Refactor code for numbering instructions into CodeGenTarget.Chris Lattner2005-01-221-10/+7
| | | | llvm-svn: 19758
* Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.Chris Lattner2005-01-021-0/+2
| | | | llvm-svn: 19243
* Add support for the isLoad and isStore flags, needed by the instruction ↵Nate Begeman2004-09-281-0/+2
| | | | | | scheduler llvm-svn: 16554
* Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAGChris Lattner2004-09-281-0/+1
| | | | llvm-svn: 16553
* Do not #include files into the llvm namespaceChris Lattner2004-08-171-2/+5
| | | | llvm-svn: 15849
* Instructions no longer need to have names.Chris Lattner2004-08-011-1/+6
| | | | llvm-svn: 15399
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