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path: root/llvm/utils/TableGen/InstrInfoEmitter.cpp
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* make ptr_rc derive from a new PointerLikeRegClass tblgen class.Chris Lattner2009-07-291-1/+1
| | | | llvm-svn: 77503
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-8/+7
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-1/+1
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-1/+2
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-1/+1
| | | | llvm-svn: 60487
* Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ↵Evan Cheng2008-10-171-1/+55
| | | | | | | | instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. TableGen has been taught to generate the lists from instruction definitions. llvm-svn: 57722
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-1/+3
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman2008-05-311-12/+0
| | | | | | | | | | | index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. llvm-svn: 51808
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-291-0/+12
| | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-281-13/+14
| | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. llvm-svn: 51660
* Move instruction flag inference out of InstrInfoEmitter and intoDan Gohman2008-04-031-133/+4
| | | | | | | | | | | | CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. llvm-svn: 49123
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-1/+2
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-1/+0
| | | | llvm-svn: 48381
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-1/+2
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner2008-01-101-2/+1
| | | | | | | | | | | | | | | | both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. llvm-svn: 45843
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-22/+33
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* if an instr lacks a pattern, assume it has side effects (unless never has ↵Chris Lattner2008-01-101-1/+4
| | | | | | s-e is true). llvm-svn: 45823
* start inferring 'no side effects'.Chris Lattner2008-01-101-54/+57
| | | | llvm-svn: 45822
* Infer mayloadChris Lattner2008-01-101-3/+13
| | | | llvm-svn: 45819
* realize that instructions who match intrinsics that read memory read memory.Chris Lattner2008-01-101-3/+12
| | | | | | Also, instructions with any nodes that are SDNPMayLoad also read memory. llvm-svn: 45817
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-081-12/+12
| | | | | | This is currently not set by anything. llvm-svn: 45748
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Rename all the M_* flags to be namespace qualified enums, and switch Chris Lattner2008-01-071-25/+25
| | | | | | | | all clients over to using predicates instead of these flags directly. These are now private values which are only to be used to statically initialize the tables. llvm-svn: 45692
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-071-3/+3
| | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. llvm-svn: 45687
* Move M_* flags down in the file. Move SchedClass up in the Chris Lattner2008-01-071-2/+2
| | | | | | | TargetInstrDescriptor class and shrink to 16-bits, saving a word in TargetInstrDescriptor. Add some comments. llvm-svn: 45686
* the name field of instructions is never set to a non-empty string, Chris Lattner2008-01-071-3/+3
| | | | | | just unconditionally use the def name of the instruction. llvm-svn: 45684
* Add predicates methods to TargetOperandInfo, and switch all clients Chris Lattner2008-01-071-3/+3
| | | | | | | over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. llvm-svn: 45677
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-2/+2
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-16/+17
| | | | llvm-svn: 45656
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-10/+22
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* set the 'isstore' flag for instructions whose pattern is an Chris Lattner2008-01-061-1/+8
| | | | | | intrinsic that writes to memory. llvm-svn: 45650
* remove some old hacky code that tried to infer whether a store Chris Lattner2008-01-061-19/+49
| | | | | | | | | | | occured in a pattern, but failed miserably. The new code works for any instruction that has a store in its pattern, including all the x86 mem op mem instructions. The only target-independent code that uses this is branch folding, so this won't change anything in practice. llvm-svn: 45648
* rearrange some code to allow inferring instr info from the pattern of the ↵Chris Lattner2008-01-061-34/+52
| | | | | | instr, but don't do so yet. llvm-svn: 45647
* final cleanups.Chris Lattner2008-01-061-4/+4
| | | | llvm-svn: 45644
* further simplifications and cleanupChris Lattner2008-01-061-37/+57
| | | | llvm-svn: 45643
* simplify some codeChris Lattner2008-01-061-16/+8
| | | | llvm-svn: 45642
* split enum emission out from InstrInfoEmitter into it's own tblgen backend.Chris Lattner2008-01-061-36/+0
| | | | llvm-svn: 45640
* tblgen shouldn't include headers from llvm codegen.Chris Lattner2007-12-301-3/+3
| | | | llvm-svn: 45429
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-2/+3
| | | | | | side effects for machine instructions. llvm-svn: 45022
* Oops. Forgot these.Evan Cheng2007-12-131-0/+1
| | | | llvm-svn: 44969
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* Added TargetInstrDescriptor::numDefs - num of results.Evan Cheng2007-08-021-1/+2
| | | | llvm-svn: 40709
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-1/+3
| | | | | | MBB's. PR1350 llvm-svn: 40518
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-101-1/+6
| | | | llvm-svn: 38498
* ImmutablePredicateOperand is no more.Evan Cheng2007-07-061-2/+1
| | | | llvm-svn: 37963
* Instructions with ImmutablePredicateOperand aren't really predicable since ↵Evan Cheng2007-07-051-1/+2
| | | | | | their predicates are fixed at isel time. llvm-svn: 37899
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
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