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* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-221-2/+2
| | | | | | correctness along the way. llvm-svn: 142726
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Add target hook for pseudo instruction expansion.Jakob Stoklund Olesen2011-09-251-0/+1
| | | | | | | | | | | | Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. llvm-svn: 140472
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-1/+2
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-2/+1
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* Follow up to r138791.Evan Cheng2011-08-301-0/+1
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Unconstify InitsDavid Greene2011-07-291-4/+4
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-4/+4
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-151-1/+1
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* Add a new field to MCOperandInfo that contains information about the type of ↵Benjamin Kramer2011-07-141-0/+5
| | | | | | | | | | the Operand. - The actual values are from the MCOI::OperandType enum. - Teach tblgen to read it from the instruction definition. - This is a better implementation of the hacks in edis. llvm-svn: 135197
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-2/+2
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson2011-07-131-2/+4
| | | | | | an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-4/+4
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-4/+4
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-2/+2
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-1/+25
| | | | llvm-svn: 134244
* Add MCInstrInfo registeration machinery.Evan Cheng2011-06-281-1/+9
| | | | llvm-svn: 134026
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+43
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-33/+33
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Remove RCBarriers from TargetInstrDesc.Evan Cheng2011-06-271-55/+1
| | | | llvm-svn: 133964
* Add support for alternative register names, useful for instructions whose ↵Owen Anderson2011-06-271-16/+18
| | | | | | | | operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-4/+4
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* - Add "Bitcast" target instruction property for instructions which performEvan Cheng2011-03-151-0/+1
| | | | | | | nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. llvm-svn: 127667
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-16/+16
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson2010-09-231-1/+0
| | | | | | | | instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! llvm-svn: 114710
* Add an TargetInstrDesc bit to indicate that a given instruction is a ↵Owen Anderson2010-09-231-0/+1
| | | | | | | | conditional move. Not intended functionality change, as nothing uses this yet. llvm-svn: 114702
* Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling2010-08-081-0/+1
| | | | | | useful after all. llvm-svn: 110531
* Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling2010-08-061-1/+0
| | | | | | | | | | | | | need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h llvm-svn: 110424
* Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling2010-07-301-0/+1
| | | | | | | later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. llvm-svn: 109901
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-1/+2
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* How about ULL...Eric Christopher2010-06-091-1/+1
| | | | llvm-svn: 105726
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-1/+1
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-72/+12
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* Teach TableGen to understand X.Y notation in the TSFlagsFields strings.Jakob Stoklund Olesen2010-03-251-1/+1
| | | | | | | Remove much horribleness from X86InstrFormats as a result. Similar simplifications are probably possible for other targets. llvm-svn: 99539
* Finally change the instruction looking map to be a densemap fromChris Lattner2010-03-191-7/+1
| | | | | | | | | record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). llvm-svn: 98916
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-2/+2
| | | | | | Use CodeGenTarget::getInstNamespace in one place and fix it. llvm-svn: 98915
* revert 98912Chris Lattner2010-03-191-2/+2
| | | | llvm-svn: 98914
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-2/+2
| | | | llvm-svn: 98912
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-2/+2
| | | | | | | to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
* Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner2010-02-101-1/+14
| | | | | | | | | for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). llvm-svn: 95753
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-1/+1
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen2010-01-151-2/+1
| | | | | | Also, DEBUG_VALUE has side effects. llvm-svn: 93498
* Add DEBUG_DECLARE. Not used yet.Dale Johannesen2010-01-091-1/+2
| | | | llvm-svn: 93040
* Add DEBUG_VALUE. Not used yet.Dale Johannesen2010-01-081-1/+2
| | | | llvm-svn: 93030
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-2/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng2009-10-011-0/+2
| | | | | | | | | | set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. llvm-svn: 83196
* Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen2009-09-281-1/+1
| | | | | | | | | | unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. llvm-svn: 83006
* prune the #includes in raw_ostream.h by moving a Chris Lattner2009-08-241-0/+1
| | | | | | | member out of line. ftostr is not particularly speedy, so that method is presumably not perf sensitive. llvm-svn: 79885
* 1. Introduce a new TargetOperandInfo::getRegClass() helper methodChris Lattner2009-07-291-0/+3
| | | | | | | | | | | | | and convert code to using it, instead of having lots of things poke the isLookupPtrRegClass() method directly. 2. Make PointerLikeRegClass contain a 'kind' int, and store it in the existing regclass field of TargetOperandInfo when the isLookupPtrRegClass() predicate is set. Make getRegClass pass this into TargetRegisterInfo::getPointerRegClass(), allowing targets to have multiple ptr_rc things. llvm-svn: 77504
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