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* [globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction ↵Daniel Sanders2017-10-311-43/+73
| | | | | | | | | | | | | | | | | | to choose a mutatable instruction. NFC Prepare for multiple instruction emission by allowing BuildMIAction to search for a suitable matcher that will support mutation. This patch deliberately neglects to add matchers aside from the root to preserve NFC. That said, it should be noted that until we support mutations other than just the opcode the chances of finding a non-root instruction for which canMutate() is true, is essentially zero. Furthermore in the presence of multi-instruction emission the chances of finding any instruction for which canMutate() is true is also zero. Nevertheless, we can't continue to require that all BuildMIAction's consider the root of the match to be recyclable due to the risk of recycling it twice in the same rule. llvm-svn: 317022
* [globalisel][tablegen] Allow any comment in DebugCommentAction. NFCDaniel Sanders2017-10-311-6/+6
| | | | llvm-svn: 317017
* [globalisel][tablegen] Fix future undefined behaviour in r316463.Daniel Sanders2017-10-241-1/+4
| | | | | | | I missed a dereference of `Matched` that preceeded the new check. Thanks to Justin Bogner for spotting it. llvm-svn: 316480
* [globalisel][tablegen] Multi-insn emission requires that BuildMIAction ↵Daniel Sanders2017-10-241-6/+6
| | | | | | | | | | | support not being linked to an InstructionMatcher. NFC When multi-instruction emission is supported, it will no longer be guaranteed that every BuildMIAction has a corresponding matched instruction. BuildMIAction should support not having one to cover the case where a rule produces more instructions than it matched. llvm-svn: 316463
* [globalisel][tablegen] Remove unused InstructionMatcher's. NFCDaniel Sanders2017-10-241-25/+12
| | | | llvm-svn: 316407
* [globalisel][tablegen] Import stores and allow GISel to automatically ↵Daniel Sanders2017-10-231-1/+79
| | | | | | | | | | | | | | | | | substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-7/+7
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* Revert MSVC 2017 build fix and fix it by moving the method that implicitly ↵Reid Kleckner2017-10-161-32/+34
| | | | | | instantiates addPredicate out of line llvm-svn: 315932
* Fix the build of GlobalISelEmitter with MSVC 2017 by specializing earlierReid Kleckner2017-10-161-12/+12
| | | | | | | MSVC doesn't seem to like implicitly instantiating addPredicate and then explicitly specializing it later. It causes an internal compiler error. llvm-svn: 315930
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-13/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-11/+5
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-161-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* [globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders2017-10-161-17/+105
| | | | | | | | | | | | | | | | | | | | | | | | MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-151-31/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-151-99/+31
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-151-31/+99
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFCDaniel Sanders2017-10-151-10/+33
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 llvm-svn: 315843
* [tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders2017-10-151-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-141-2/+2
| | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters. llvm-svn: 315826
* [globalisel][tablegen] Simplify named operand/operator lookups and fix a ↵Daniel Sanders2017-10-141-69/+128
| | | | | | | | | | | | | | | | | | | | | | wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
* [globalisel][tablegen] Fix a use-after free bug that manifests on non-macOS ↵Daniel Sanders2017-10-131-1/+1
| | | | | | machines. llvm-svn: 315765
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-131-19/+83
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 ↵Daniel Sanders2017-10-131-26/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use them. Summary: The purpose of this patch is to expose more information about ImmLeaf-like PatLeaf's so that GlobalISel can learn to import them. Previously, ImmLeaf could only be used to test int64_t's produced by sign-extending an APInt. Other tests on immediates had to use the generic PatLeaf and extract the constant using C++. With this patch, tablegen will know how to generate predicates for APInt, and APFloat. This will allow it to 'do the right thing' for both SelectionDAG and GlobalISel which require different methods of extracting the immediate from the IR. This is NFC for SelectionDAG since the new code is equivalent to the previous code. It's also NFC for FastISel because FastIselShouldIgnore is 1 for the ImmLeaf subclasses. Enabling FastIselShouldIgnore == 0 for these new subclasses will require a significant re-factor of FastISel. For GlobalISel, it's currently NFC because the relevant code to import the affected rules is not yet present. This will be added in a later patch. Depends on D36086 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: bjope, aemerson, rengolin, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36534 llvm-svn: 315747
* [globalisel] Add support for ValueType operands in patterns.Daniel Sanders2017-10-091-1/+9
| | | | | | | | | | | | It's rare but there are a small number of patterns like this: (set i64:$dst, (add i64:$src1, i64:$src2)) These should be equivalent to register classes except they shouldn't check for a specific register bank. This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other in-tree targets such as BPF. llvm-svn: 315226
* [globalisel] Add support for intrinsic_w_chain.Daniel Sanders2017-09-191-3/+5
| | | | | | This maps directly to G_INTRINSIC_W_SIDE_EFFECTS. llvm-svn: 313627
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-17/+24
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* [globalisel][tablegen] Predicates should start from GIPFP_Invalid+1 not ↵Daniel Sanders2017-08-241-2/+4
| | | | | | | | | GIPFP_Invalid This fixes a warning when there are zero defined predicates and also fixes an unnoticed bug where the first predicate in the table was unusable. llvm-svn: 311684
* Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-241-13/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 The previous commit was reverted for breaking the build but this appears to have been the recurring problem on the Windows bots with tablegen not being re-run when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a build with clean=True should fix it but this string should do this in advance: Requires a clean build. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311645
* Revert r311546 as it breaks buildVictor Leschuk2017-08-231-124/+13
| | | | | | http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4394 llvm-svn: 311560
* [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-231-13/+124
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311546
* [globalisel][tablegen] Add tests for FeatureBitsets and ComplexPattern ↵Daniel Sanders2017-08-231-3/+6
| | | | | | predicates. llvm-svn: 311542
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-171-33/+29
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 311084
* Re-commit: [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-171-40/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
* Revert r310919 - [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-151-100/+60
| | | | | | | | | | As expected, this failed on the windows bots but the instrumentation showed something interesting. The ADD8ri and INC8r rules are never directly compared on the windows machines. That implies that the issue lies in transitivity of the Compare predicate. I believe I've already verified that but maybe I missed something. llvm-svn: 310922
* Re-commit with some instrumentation: [globalisel][tablegen] Support ↵Daniel Sanders2017-08-151-60/+100
| | | | | | | | | | | | | | | | | | | | | | | | | zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on the windows bots and this one is likely to fail on those same bots. However, the added instrumentation should reveal a particular isHigherPriorityThan() evaluation which I'm expecting to expose that these machines are weighing priority of two rules differently from the non-windows machines. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 310919
* Revert r310716 (and r310735): [globalisel][tablegen] Support ↵Daniel Sanders2017-08-111-65/+50
| | | | | | | | | | | zero-instruction emission. Two of the Windows bots are failing test\CodeGen\X86\GlobalISel\select-inc.mir which should not have been affected by the change. Reverting while I investigate. Also reverted r310735 because it builds on r310716. llvm-svn: 310745
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-111-33/+29
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 310735
* [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-111-25/+44
| | | | | | | | | | | | | | | | | | | Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. Depends on D35833 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 310716
* [globalisel][tablegen] Remove unnecessary ; to satisfy ubuntu-gcc7.1-werror.Daniel Sanders2017-08-081-1/+1
| | | | llvm-svn: 310357
* [globalisel][tablegen] Add support for importing 'imm' operands.Daniel Sanders2017-08-081-15/+122
| | | | | | | | | | | | | | | | | | | Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
* [GlobalISel] Only merge memory ops for mayLoad or mayStore instrs.Florian Hahn2017-08-031-18/+21
| | | | | | | | | | | | | | | | Summary: We only need to merge memory operands for instructions that access memory. This slightly reduces the number of actions executed. Reviewers: MatzeB, rovka, dsanders Reviewed By: dsanders Subscribers: aemerson, igorb, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36151 llvm-svn: 309944
* [globalisel][tablegen] Do not merge memoperands from instructions that ↵Daniel Sanders2017-08-021-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | weren't in the match. Summary: Fix a bug discovered in an out-of-tree target where memoperands from pseudo-instructions that weren't part of the match were being merged into the result instructions as part of GIR_MergeMemOperands. This bug was caused by a change to the handling of State.MIs between rules when the state machine tables were fused into a single table. Previously, each rule would reset State.MIs using State.MIs.resize(1) but this is no longer done, as a result stale data is occasionally left in some elements of State.MIs. Most opcodes aren't affected by this but GIR_MergeMemOperands merges all memoperands from the intructions recorded in State.MIs into the result instruction. Suppose for example, we processed but rejected the following pattern: (signextend (load x)) at this point, State.MIs contains the signextend and the load. Now suppose we process and accept this pattern: (add x, y) at this point, State.MIs contains the add as well as the (now irrelevant) load. When GIR_MergeMemOperands is processed, the memoperands from that irrelevant load will be merged into the result instruction even though it was not part of the match. Bringing back the State.MIs.resize(1) would fix the problem but it would limit our ability to optimize the table in the future. Instead, this patch fixes the problem by explicitly stating which instructions should be merged into the result. There's no direct test case in this commit because a test case would be very brittle. However, at the time of writing this should fix the failures in http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/ as well as a failure in test/CodeGen/ARM/GlobalISel/arm-isel.ll when expensive checks are enabled. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: fhahn, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36094 llvm-svn: 309804
* [globalisel][tablegen] Ensure MatchTable's are compile-time constants with ↵Daniel Sanders2017-07-271-1/+1
| | | | | | | | | constexpr. NFC. This should prevent any re-occurence of the problem where the table was initialized at run-time. llvm-svn: 309267
* Re-commit: r309094 [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-271-28/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that we have control flow in place, fuse the per-rule tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. This is NFC in terms of externally visible behaviour but some internals have changed slightly. State.MIs is no longer reset between each rule that is attempted because it's not necessary to do so. As a consequence of this the restriction on the order that instructions are added to State.MIs has been relaxed to only affect recorded instructions that require new elements to be added to the vector. GIM_RecordInsn can now write to any element from 1 to State.MIs.size() instead of just State.MIs.size(). The compile-time regressions from the last commit were caused by the ARM target including a non-const variable (zero_reg) in the table and therefore generating an initializer for it. That variable is now const. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35681 llvm-svn: 309264
* Revert r309094: [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-261-26/+28
| | | | | | | | The ARM bots have started failing and while this patch should be an improvement for these bots, it's also the only suspect in the blamelist. Reverting while Diana and I investigate the problem. llvm-svn: 309111
* [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-261-28/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that we have control flow in place, fuse the per-rule tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. This is NFC in terms of externally visible behaviour but some internals have changed slightly. State.MIs is no longer reset between each rule that is attempted because it's not necessary to do so. As a consequence of this the restriction on the order that instructions are added to State.MIs has been relaxed to only affect recorded instructions that require new elements to be added to the vector. GIM_RecordInsn can now write to any element from 1 to State.MIs.size() instead of just State.MIs.size(). Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35681 llvm-svn: 309094
* [globalisel][tablegen] Add control-flow to the MatchTable.Daniel Sanders2017-07-201-119/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This will allow us to merge the various sub-tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. The bulk of this patch is a mechanical conversion to the new MatchTable object which is responsible for tracking label definitions and filling in the index of the jump targets. It is also responsible for nicely formatting the table. This was necessary to support the new GIM_Try opcode which takes the index to jump to if the match should fail. This value is unknown during table construction and is filled in during emission. To support nesting try-blocks (although we currently don't emit tables with nested try-blocks), GIM_Reject has been re-introduced to explicitly exit a try-block or fail the overall match if there are no active try-blocks. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35117 llvm-svn: 308596
* [globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is ↵Daniel Sanders2017-07-111-7/+11
| | | | | | | | | | | | | | | | | | | | | | used on multiple insns. In each rule, each use of ComplexPattern is assigned an element in the Renderers array. The matcher then collects renderer functions in this array and they are used to render instructions. This works well for a single instruction but a bug in the allocation mechanism causes the elements to be assigned on a per-instruction basis rather than a per-rule basis. So in the case of: (set GPR32:$dst, (Op complex:$src1, complex:$src2)) tablegen currently assigns elements 0 and 1 to $src1 and $src2 respectively, but for: (set GPR32:$dst, (Op complex:$src1, (Op complex:$src2))) it currently assigned both $src1 and $src2 the same element (0). This results in one complex operand being rendered twice and the other being forgotten. This patch corrects the allocation such that $src1 and $src2 are still allocated different elements in this case. llvm-svn: 307646
* [globalisel][tablegen] Correct matching of intrinsic ID's.Daniel Sanders2017-07-111-6/+23
| | | | | | | | | | | | TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
* [globalisel][tablegen] Rename and re-comment render functions to match the ↵Daniel Sanders2017-07-061-7/+7
| | | | | | | | | | new MatchTables. NFC. The conversion to MatchTable left the function names and comments referring to C++ statements and expressions. Updated the names and comments to account for the fact that they're no longer unconstrained statements/expressions. llvm-svn: 307248
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