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path: root/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
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* Add support for positionally-encoded operands to FixedLenDecoderEmitterHal Finkel2013-12-191-4/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, the PowerPC instruction definitions make heavy use of the positional operand encoding heuristic to map operands onto bitfield variables in the instruction definitions. Changing this to use name-based mapping is not trivial, however, because additional infrastructure needs to be designed to handle mapping of complex operands (with multiple suboperands) onto multiple bitfield variables. In the mean time, this adds support for positionally encoded operands to FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC backend. To prevent an accidental reliance on this feature, and to prevent an undesirable interaction with existing disassemblers, a backend must opt-in to this support by setting the new decodePositionallyEncodedOperands instruction-set bit to true. When enabled, this iterates the variables that contribute to the instruction encoding, just as the encoder does, and emulates the procedure the encoder uses to map "numbered" operands to variables. The bit range for each variable is also determined as the encoder determines them. This map is then consulted during the decoder-generator's loop over operands to decode, allowing the decoder to understand both position-based and name-based operand-to-variable mappings. As noted in the comment on the decodePositionallyEncodedOperands definition, this support should be removed once it is no longer needed. There should be no change to existing disassemblers. llvm-svn: 197691
* Add support for PointerLikeRegClass to FixedLenDecoderEmitterHal Finkel2013-12-191-0/+4
| | | | | | | | This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter should recognize PointerLikeRegClass operands as register types, and generate register-like decoding calls instead of treating them like immediates. llvm-svn: 197680
* Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel2013-12-171-0/+2
| | | | | | | | | | | | | | | The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
* Remove several unused variables.Rafael Espindola2013-10-011-1/+0
| | | | | | Patch by Alp Toker. llvm-svn: 191757
* Teaching llvm-tblgen to not emit a switch statement when there are no case ↵Aaron Ballman2013-07-151-8/+13
| | | | | | statements. llvm-svn: 186330
* TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in ↵NAKAMURA Takumi2012-12-261-1/+1
| | | | | | | | fieldFromInstruction(). Reported by Yang Yongyong, thanks! llvm-svn: 171101
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-4/+3
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-1/+2
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-101-2/+2
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-6/+6
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.Sean Silva2012-10-051-1/+1
| | | | | | | | This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of these uses are actually more like isa<> or cast<>, and will be changed to the semanticaly appropriate one in a future patch. llvm-svn: 165291
* TableGen: Add initializer.Jim Grosbach2012-09-171-1/+1
| | | | | | | Keep GCC's warnings happy. It can't reason out that the state machine won't ever hit the potentially uninitialized use in OPC_FilterValue. llvm-svn: 164041
* Re-work bit/bits value resolving in tblgenMichael Liao2012-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. llvm-svn: 163360
* Declare some for loop indices inside the for loop statement.Craig Topper2012-08-171-20/+13
| | | | llvm-svn: 162085
* Fix up indentation of outputted decode function for readability.Craig Topper2012-08-171-8/+8
| | | | llvm-svn: 162082
* Fix a const violation in the generated disassembler.Benjamin Kramer2012-08-151-2/+2
| | | | llvm-svn: 161940
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-281/+722
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-1/+84
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Second part for the 153874 oneSilviu Baranga2012-04-021-3/+3
| | | | llvm-svn: 153875
* More const-correcting of FixedLenDecoderEmitter.Craig Topper2012-03-161-13/+17
| | | | llvm-svn: 152906
* Const-correct the FixedLenDecoderEmitter. Pass a few things by const ↵Craig Topper2012-03-161-53/+58
| | | | | | reference instead of value to avoid some copying. llvm-svn: 152899
* Spacing fixes. Mostly aligning arguments that spilled onto next line with ↵Craig Topper2012-03-161-37/+36
| | | | | | the opening parenthese instead of 2 spaces in. llvm-svn: 152889
* Remove unused field NumVariable from Filter class. Even it was needed the ↵Craig Topper2012-03-161-9/+3
| | | | | | same result could be found with VariableInstructions.size(). Also fix some typos in comments. llvm-svn: 152885
* Remove unused field from FixedLenDecoderEmitter. Move NumberedInstructions ↵Craig Topper2012-03-131-1/+2
| | | | | | declaration from class to run method since its only used there and was being reinitialized anyway. llvm-svn: 152616
* Tidy up. 80 columns.Jim Grosbach2012-02-291-13/+21
| | | | llvm-svn: 151764
* Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy2012-02-091-2/+76
| | | | | | UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. llvm-svn: 150169
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-9/+7
| | | | llvm-svn: 149814
* Fix unused variable warning in the rare circumstance that we have no ↵Owen Anderson2011-10-171-1/+4
| | | | | | feature-dependent instructions. llvm-svn: 142193
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Subtarget getFeatureBits() returns a uint64_t, not unsigned.Bob Wilson2011-10-011-1/+1
| | | | llvm-svn: 140928
* Make sure to handle the case where emitPredicateMatch returns false. ↵Eli Friedman2011-09-081-1/+2
| | | | | | Noticed by inspection. llvm-svn: 139317
* Fix warning on windows; use of comparison with bool argument.James Molloy2011-09-081-1/+1
| | | | llvm-svn: 139286
* Fix a use of freed string contents.Andrew Trick2011-09-081-4/+4
| | | | | | Speculatively try to fix our windows testers with a patch I found on the internet. llvm-svn: 139279
* whitespaceAndrew Trick2011-09-081-2/+2
| | | | llvm-svn: 139278
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy2011-09-071-4/+52
| | | | | | predicate checking to the Disassembler. llvm-svn: 139250
* Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson2011-08-171-16/+22
| | | | | | | | instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. llvm-svn: 137830
* Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly ↵Owen Anderson2011-08-091-2/+2
| | | | | | checking the success result of custom decoder hooks on singleton decodings. llvm-svn: 137171
* Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for ↵Owen Anderson2011-08-011-5/+9
| | | | | | encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers. llvm-svn: 136660
* The FixedLenDecoder needs to gracefully handle failing per-instruction ↵Owen Anderson2011-08-011-3/+3
| | | | | | decoder hooks in addition to per-operand decoder hooks. llvm-svn: 136645
* Enhance the fixed length disassembler to better handle operand decoding ↵Owen Anderson2011-08-011-2/+2
| | | | | | failures. llvm-svn: 136635
* Correctly handle scattered operands where the bits of the operand are ↵Owen Anderson2011-07-291-0/+5
| | | | | | contiguous, but out of order. llvm-svn: 136534
* Unconstify InitsDavid Greene2011-07-291-17/+16
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-16/+17
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Third time's the charm for implementing tied operand decoding properly.Owen Anderson2011-07-291-6/+6
| | | | llvm-svn: 136478
* Fix a case where, when trying to track tied operands, we'd accidentally ↵Owen Anderson2011-07-291-3/+3
| | | | | | overwrite our mapping. llvm-svn: 136467
* Enhance the fixed-length decoder emitter to support tied operands.Owen Anderson2011-07-281-1/+13
| | | | llvm-svn: 136431
* Enhance the fixed-length decoder emitter to support parsing scattered fields.Owen Anderson2011-07-281-76/+91
| | | | llvm-svn: 136405
* Enhance the FixedLengthDecoder to be able to generate plausible-looking ↵Owen Anderson2011-07-191-108/+125
| | | | | | decoders for ARM. llvm-svn: 135524
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-17/+16
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-16/+17
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
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